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參數(shù)資料
| 型號(hào)： | AD9552BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN LP 32LFCSP |
| 設(shè)計(jì)資源： | Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 900MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
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Data Sheet
AD9552
Rev. E | Page 25 of 32
PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)
Table 19.
Address
Bit
Bit Name
Description
0x0A
[7:0]
Charge pump current control
These bits set the magnitude of the PLL charge pump current. The granularity is
~3.5 μA with a full-scale magnitude of ~900 μA. Register 0x0A is ineffective unless
Register 0x0B[7] = 1. Default is 0x80, or ~448 μA.
0x0B
7
Enable SPI control of charge
pump current
Controls functionality of Register 0x0A.
0 = the device automatically controls the charge pump current (default).
1 = charge pump current defined by Register 0x0A.
6
Enable SPI control of
antibacklash period
Controls functionality of Register 0x0D[7:6].
0 = the device automatically controls the antibacklash period (default).
1 = antibacklash period defined by Register 0x0D[7:6].
[5:4]
CP mode
Controls the mode of the PLL charge pump.
00 = tristate.
01 = pump up.
10 = pump down.
11 = normal (default).
3
Enable CP mode control
Controls functionality of Bits[5:4] (CP mode).
0 = the device automatically controls the charge pump mode (default).
1 = charge pump mode is defined by Bits[5:4].
2
PFD feedback input edge control
Selects the polarity of the active edge of the PLL’s feedback input.
0 = positive edge (default).
1 = negative edge.
1
PFD reference input edge control
Selects the polarity of the active edge of the PLL’s reference input.
0 = positive edge (default).
1 = negative edge.
0
Force VCO to midpoint frequency
Selects VCO control voltage functionality.
0 = normal VCO operation (default).
1 = force VCO control voltage to midscale.
0x0C
7
Unused
Unused.
6
CP offset current polarity
Selects the polarity of the charge pump offset current of the PLL. This bit is ineffective
unless Bit 3 = 1.
0 = pump up (default).
1 = pump down.
[5:4]
CP offset current
Controls the magnitude of the charge pump offset current of the PLL as a fraction of
the value in Register 0x0A. This bit is ineffective unless Bit 3 = 1.
00 = 1/2 (default).
01 = 1/4.
10 = 1/8.
11 = 1/16.
3
Enable CP offset current control
Controls functionality of Bits[6:4].
0 = the device automatically controls charge pump offset current (default).
1 = charge pump offset current defined by Bits[6:4].
2:0
Reserved
0x0D
[7:6]
Antibacklash control
Controls the PFD antibacklash period of the PLL. These bits are ineffective unless
Register 0x0B[6] = 1.
00 = minimum (default).
01 = low.
10 = high.
11 = maximum.
[5:1]
Unused
Unused.
0
PLL lock detector power-down
Controls power-down of the PLL lock detector.
0 = lock detector active (default).
1 = lock detector powered down.
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