參數(shù)資料
型號(hào)： AD9552BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 0K
描述： IC PLL CLOCK GEN LP 32LFCSP
設(shè)計(jì)資源： Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
標(biāo)準(zhǔn)包裝： 1,500
類型： 時(shí)鐘發(fā)生器
PLL： 帶旁路
輸入： 時(shí)鐘，晶體
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 900MHz
除法器/乘法器： 是/無
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
AD9552
Data Sheet
Rev. E | Page 26 of 32
VCO Control (Register 0x0E to Register 0x10)
Table 20.
Address
Bit
Bit Name
Description
0x0E
7
Calibrate VCO
Initiates VCO calibration (this is an autoclearing bit). This bit is ineffective unless Bit 2 = 1.
6
Enable ALC
Enables automatic level control (ALC) of the VCO.
0 = Register 0x0F[7:2] defines the VCO level.
1 = the device automatically controls the VCO level (default).
[5:3]
ALC threshold
Controls the VCO ALC threshold detector level from minimum (000) to maximum
(111).
The default is 110.
2
Enable SPI control of VCO
calibration
Enables functionality of Bit 71.
0 = the device automatically performs VCO calibration (default).
1 = Bit 7 controls VCO calibration.
1
Boost VCO supply
Selects VCO supply voltage.
0 = normal supply voltage (default).
1 = increase supply voltage by 100 mV.
0
Enable SPI control of VCO band
setting
Controls VCO band setting functionality.
0 = the device automatically selects the VCO band (default).
1 = VCO band defined by Register 0x10[7:1].
0x0F
[7:2]
VCO level control
Controls the VCO amplitude from minimum (00 0000) to maximum (11 1111). The
default is 10 0000.
These bits are ineffective unless 0x0E[6] = 0.
[1:0]
Unused
Unused.
0x10
[7:1]
VCO band control
Controls the VCO frequency band from minimum (000 0000) to maximum (111 1111).
The default is 100 0000.
0
Unused
Unused.
1 An I/O update must be asserted after setting this bit and before issuing a SPI-controlled VCO calibration (writing 1 to Register 0x0E, Bit 7).
PLL Control (Register 0x11 to Register 0x19)
Table 21.
Address
Bit
Bit Name
Description
0x11
[7:0]
N
The 8-bit integer divide value for the SDM. Default is 0x00.
Note that operational limitations impose a lower boundary of 64 (0x40) on N.
0x12
[7:0]
MOD
Bits[19:12] of the 20-bit modulus of the SDM.
0x13
[7:0]
MOD
Bits[11:4] of the 20-bit modulus of the SDM.
0x14
[7:4]
MOD
Bits[3:0] of the 20-bit modulus of the SDM.
Default is MOD = 1000 0000 0000 0000 0000 (524,288).
3
Enable SPI control of
output frequency
Controls output frequency functionality.
0 = output frequency defined by the Y[3:0] pins (default).
1 = contents of Register 0x11 to Register 0x17 define output frequency via N, MOD, and FRAC.
2
Bypass SDM
Controls bypassing of the SDM.
0 = allow integer-plus-fractional division (default).
1 = allow only integer division.
1
Disable SDM
Controls the SDM internal clocks.
0 = normal operation (SDM clocks active) (default).
1 = SDM disabled (SDM clocks stopped).
0
Reset PLL
Controls initialization of the PLL.
0 = normal operation (default).
1 = resets the counters and logic associated with the PLL but does not affect the output dividers.
0x15
[7:0]
FRAC
Bits[19:12] of the 20-bit fractional part of the SDM.
0x16
[7:0]
FRAC
Bits[11:4] of the 20-bit fractional part of the SDM.
0x17
[7:4]
FRAC
Bits[3:0] of the 20-bit fractional part of the SDM.
Default is FRAC = 0010 0000 0000 0000 0000 (131,072).
[3:1]
Unused
Write zeros to these bits when programming this register.
0
P
1 divider
Bit 5 of the 6-bit P
1 divider for OUT1.
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