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參數(shù)資料
| 型號： | AD9522-4BCPZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 75/84頁 |
| 文件大?。?/td> | 1606K |
| 代理商： | AD9522-4BCPZ-REEL7 |
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AD9522-4
Rev. 0 | Page 77 of 84
Reg.
Addr
(Hex) Bit(s) Name
Description
198
[2]
Channel 2 power-down
Channel 2 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into the high
impedance power-down mode by setting this bit.)
198
[0]
Disable Divider 2 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
199
[7:4]
Divider 3 low cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
low. A value of 0x0 means the divider is low for one input clock cycle (default: 0x0).
199
[3:0]
Divider 3 high cycles
Number of clock cycles (minus 1) of the divider input during which the divider output stays
high. A value of 0x0 means the divider is high for one input clock cycle (default: 0x0).
19A
[7]
Divider 3 bypass
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
19A
[6]
Divider 3 ignore SYNC
Ignore SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
19A
[5]
Divider 3 force high
Forces divider output to high. This requires that ignore SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
19A
[4]
Divider 3 start high
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
19A
[3:0]
Divider 3 phase offset
Phase offset (default: 0x0).
19B
[2]
Channel 3 power-down
Channel 3 powers down.
[2] = 0; normal operation (default).
[2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into the high
impedance power-down mode by setting this bit.)
19B
[0]
Disable Divider 3 DCC
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Table 55. VCO Divider and CLK Input
Reg.
Addr
(Hex) Bit(s) Name
Description
1E0
[2:0]
VCO divider
[2]
[1]
[0]
Divide
0
2 (default)
0
1
3
0
1
0
4
0
1
5
1
0
6
1
0
1
Output static
1
0
1 (bypass)
1
Output static
1E1
[4]
Power-down clock input section
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
[4] = 0; normal operation (default).
[4] = 1; power down.
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