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參數(shù)資料
| 型號： | AD9522-4BCPZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 7/84頁 |
| 文件大小： | 1606K |
| 代理商： | AD9522-4BCPZ-REEL7 |
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AD9522-4
Rev. 0 | Page 15 of 84
POWER DISSIPATION
Table 18.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER DISSIPATION, CHIP
Does not include power dissipated in external resistors; all LVDS
outputs terminated with 100 Ω across differential pair; all CMOS
outputs have 10 pF capacitive loading
Power-On Default
0.88
1.0
W
No clock; no programming; default register values
PLL Locked; One LVDS Output Enabled
0.54
0.63
W
fREF = 25 MHz; fOUT = 250 MHz; VCO = 1500 MHz; VCO divider = 2;
one LVDS output and output divider enabled; zero delay off;
ICP = 4.8 mA
PLL Locked; One CMOS Output Enabled
0.55
0.66
W
fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 1500 MHz; VCO divider = 2;
one CMOS output and output divider enabled; zero delay off;
ICP = 4.8 mA
Distribution Only Mode; VCO Divider On;
One LVDS Output Enabled
0.36
0.43
W
fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVDS output
and output divider enabled; zero delay off
Distribution Only Mode; VCO Divider Off;
One LVDS Output Enabled
0.33
0.4
W
fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider bypassed; one LVDS
output and output divider enabled; zero delay off
Maximum Power, Full Operation
1.1
1.3
W
PLL on; internal VCO = 1500 MHz; VCO divider = 2; all channel
dividers on; 12 LVDS outputs @ 125 MHz; zero delay on
PD Power-Down
35
50
mW
PD pin pulled low; does not include power dissipated in
termination resistors
PD Power-Down, Maximum Sleep
27
43
mW
PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; power-
down SYNC, 0x230[2] = 1b; power-down distribution reference,
0x230[1] = 1b
VCP Supply
8
2.3
mW
PLL operating; typical closed-loop configuration
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power delta when a function is enabled/disabled
VCO Divider On/Off
33
43
mW
VCO divider not used
REFIN (Differential) Off
25
31
mW
Delta between reference input off and differential reference
input mode
REF1, REF2 (Single-Ended) On/Off
16
22
mW
Delta between reference inputs off and one singled-ended
reference enabled; double this number if both REF1 and REF2
are powered up
VCO On/Off
60
95
mW
Internal VCO disabled; CLK input selected
PLL Dividers and Phase Detector On/Off
54
67
mW
PLL off to PLL on, normal operation; no reference enabled
LVDS Channel
118
146
mW
No LVDS output on to one LVDS output on; channel divider set to 1
LVDS Driver
11
15
mW
Second LVDS output turned on, same channel
CMOS Channel
120
154
mW
No CMOS output on to one CMOS output on; channel divider
set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading
CMOS Driver On/Off
16
30
mW
Additional CMOS outputs within the same channel turned on
Channel Divider Enabled
33
40
mW
Delta between divider bypassed (divide-by-1) and divide-by-2 to
divide-by-32
Zero Delay Block On/Off
30
35
mW
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9522-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12 LVDS/24 CMOS Output Clock Generator |
| AD9522-5/PCBZ | 功能描述:BOARD EVALUATION FOR AD9522-5 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9522-5BCPZ | 功能描述:IC CLOCK GEN 2.4GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
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