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參數(shù)資料
| 型號： | AD9522-4BCPZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 56/84頁 |
| 文件大?。?/td> | 1606K |
| 代理商： | AD9522-4BCPZ-REEL7 |
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AD9522-4
Rev. 0 | Page 6 of 84
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
PHASE OFFSET IN ZERO DELAY
REF refers to REFIN (REF1)/REFIN (REF2)
Phase Offset (REF-to-LVDS Clock Output
Pins) in Internal Zero Delay Mode
1890
2348
3026
ps
When N delay and R delay are bypassed
Phase Offset (REF-to-LVDS Clock Output
Pins) in Internal Zero Delay Mode
900
1217
1695
ps
When N delay = Setting 111 and R delay is bypassed
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
318
677
1085
ps
When N delay and R delay are bypassed
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
329
+33
+360
ps
When N delay = Setting 011 and R delay is bypassed
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the value
of the N divider)
@ 500 kHz PFD Frequency
165
dBc/Hz
@ 1 MHz PFD Frequency
162
dBc/Hz
@ 10 MHz PFD Frequency
152
dBc/Hz
@ 50 MHz PFD Frequency
144
dBc/Hz
PLL Figure of Merit (FOM)
222
dBc/Hz
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure of
merit decreases with decreasing slew rate; see Figure 12
PLL DIGITAL LOCK DETECT WINDOW2
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings; lock
detect window settings can be varied by changing the
CPRSET resistor
Lock Threshold (Coincidence of Edges)
Selected by 0x017[1:0] and 0x018[4] (this is the threshold
to go from unlock to lock)
Low Range (ABP 1.3 ns, 2.9 ns)
3.5
ns
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
7.5
ns
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
High Range (ABP 6.0 ns)
3.5
ns
0x017[1:0] = 10b; 0x018[4] = 0b
Unlock Threshold (Hysteresis)2
Selected by 0x017[1:0] and 0x018[4] (this is the threshold
to go from lock to unlock)
Low Range (ABP 1.3 ns, 2.9 ns)
7
ns
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b
High Range (ABP 1.3 ns, 2.9 ns)
15
ns
0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b
High Range (ABP 6.0 ns)
11
ns
0x017[1:0] = 10b; 0x018[4] = 0b
1 The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
2 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
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