參數(shù)資料
型號： AD9522-4BCPZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： OTHER CLOCK GENERATOR, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù)： 37/84頁
文件大?。?/td> 1606K
代理商： AD9522-4BCPZ-REEL7
AD9522-4
Rev. 0 | Page 42 of 84
DIVIDE BY 1,
2, 3, 4, 5, OR 6
LF
CLK/CLK
R
DIVIDER
R
DELAY
N
DIVIDER
N
DELAY
PFD
CP
LOOP
FILTER
MUX1
REG 0x01E[1] = 1
0
1
REFIN/
REFIN
MU
X
3
REG 0x01E[0]
ZERO DELAY
INTERNAL FEEDBACK PATH
EXTERNAL FEEDBACK PATH
ZERO DELAY FEEDBACK CLOCK
CHANNEL DIVIDER 0
CHANNEL DIVIDER 1
CHANNEL DIVIDER 2
CHANNEL DIVIDER 3
OUT0 TO OUT2
OUT3 TO OUT5
OUT6 TO OUT8
OUT9 TO OUT11
AD9522
0
72
25
-05
3
Figure 49. Zero Delay Function
ZERO DELAY OPERATION
Zero delay operation aligns the phase of the output clocks with
the phase of the external PLL reference input. There are two
zero delay modes on the AD9522: internal and external.
Internal Zero Delay Mode
The internal zero delay function of the AD9522 is achieved by
feeding the output of Channel Divider 0 back to the PLL N
divider. In Figure 49, the change in signal routing for internal
zero delay mode is shown in blue.
Set Register 0x01E[2:1] = 01b to select internal zero delay mode.
In the internal zero delay mode, the output of Channel Divider 0 is
routed back to the PLL (N divider) through Mux3 and Mux1
(feedback path shown in blue in Figure 49). The PLL synchronizes
the phase/edge of the output of Channel Divider 0 with the
phase/edge of the reference input.
Because the channel dividers are synchronized to each other,
the outputs of the channel divider are synchronous with the
reference input. Both the R delay and the N delay inside the
PLL can be programmed to compensate for the propagation
delay from the output drivers and PLL components to minimize
the phase offset between the clock output and the reference
input to achieve zero delay.
External Zero Delay Mode
The external zero delay function of the AD9522 is achieved by
feeding one clock output back to the CLK input and ultimately
back to the PLL N divider. In Figure 49, the change in signal
routing for external zero delay mode is shown in red.
Setting 0x01E[2:1] = 11b to select the external zero delay mode .
In external zero delay mode, one of the twelve output clocks
(OUT0 to OUT11) can be routed back to the PLL (N divider)
through the CLK/CLK pins and through Mux3 and Mux1. This
feedback path is shown in red in
.
The user must specify which channel divider will be used for
external zero delay mode in order for VCO calibration to work
correctly. Channel Divider 0 is the default. Channel Divider 1,
Channel Divider 2, or Channel Divider 3 can be selected for
zero delay feedback by changing the value in Register 0x01E[4:3].
The PLL synchronizes the phase/edge of the feedback output clock
with the phase/edge of the reference input. Because the channel
dividers are synchronized to each other, the clock outputs are
synchronous with the reference input. Both the R delay and the
N delay inside the PLL can be programmed to compensate for
the propagation delay from the PLL components to minimize the
phase offset between the feedback clock and the reference input.
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