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參數(shù)資料
| 型號： | AD7725BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT PROG 44MQFP |
| 產(chǎn)品變化通告： | AD7725BSZ Discontinuation 16/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 900k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，雙極 |
| 配用： | EVAL-AD7725CBZ-ND - BOARD EVALUATION FOR AD7725 |
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REV. A
AD7725
–15–
CIRCUIT DESCRIPTION
The AD7725 employs a
- conversion technique to convert
the analog input into an equivalent digital word. The modulator
samples the input waveform and outputs an equivalent digital
word at the input clock frequency, fCLKIN.
Due to the high oversampling rate, which spreads the quantiza-
tion noise from 0 to fCLKIN/2, the noise energy contained in the
band of interest is reduced (Figure 9a). To further reduce the
quantization noise, a high order modulator is employed to shape
the noise spectrum so that most of the noise energy is shifted
out of the band of interest (Figure 9b).
The digital filtering that follows the modulator removes the
large out-of-band quantization noise (Figure 9c) while also
reducing the data rate from fCLKIN at the input of the filter to
fCLKIN/16 or less at the output of the filter, depending on the
filter type used.
Digital filtering has certain advantages over analog filtering.
Because digital filtering occurs after the A/D conversion, it can
remove noise injected during the conversion process. Analog
filtering cannot do this. The digital filter also has a linear
phase response.
a.
b.
c.
QUANTIZATION NOISE
NOISE SHAPING
DIGITAL FILTER CUTOFF FREQUENCY
fCLKIN/2
BAND OF INTEREST
Figure 9.
-
ADC
The AD7725 employs three fixed finite impulse response (FIR)
filters in series. Each individual filter’s output data rate is half
that of its input data rate. The fourth stage is programmable;
the user can select a range of different filter responses at this
stage. Both the filter response and the decimation are user pro-
grammable. See the Filtering section for more details.
APPLYING THE AD7725
Analog Input Range
The AD7725 has differential inputs to provide common-mode
noise rejection. In unipolar mode, the analog input is single-
ended and its range is 0 V to (8/5
VREF2). In bipolar mode,
the analog input is single-ended or differential, and its input
range is
±(4/5
VREF2). The output code is twos complement
in both modes with 1 LSB = 61
V.
The ideal input/output transfer characteristics for the two
modes are shown in Figure 10. In both modes, the absolute
voltage on each input must remain within the supply range
AGND to AVDD. Bipolar mode allows either single-ended or
differential input signals while unipolar mode allows single-
ended signals.
DIFFERENTIAL INPUT VOLTAGE, V IN(+) – V IN(–)
011...111
–4/5
VREF2
(0V)
0V
(4/5
VREF2)
OUTPUT
CODE
4/5
VREF2 – 1LSB
BIPOLAR
(8/5
VREF2 – 1LSB)
UNIPOLAR
011...110
000...010
000...001
000...000
111...111
111...110
100...001
100...000
Figure 10. Bipolar/(Unipolar) Mode Transfer Function
The AD7725 will accept full-scale inband signals; however,
large scale out-of-band signals can overload the modulator inputs.
A minimal single-pole RC antialias filter set to fCLKIN/24 will allow
full-scale input signals over the entire frequency spectrum.
Analog Input
The analog input of the AD7725 uses a switched capacitor
technique to sample the input signal. For the purpose of driving
the AD7725, an equivalent circuit of the analog inputs is shown
in Figure 11. For each half-clock cycle, two highly linear sam-
pling capacitors are switched to both inputs, converting the
input signal into an equivalent sampled charge. A signal source
driving the analog inputs must be able to source this charge,
while also settling to the required accuracy by the end of each
half-clock phase.
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