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參數(shù)資料
| 型號： | AD7725BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT PROG 44MQFP |
| 產(chǎn)品變化通告： | AD7725BSZ Discontinuation 16/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 900k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7725CBZ-ND - BOARD EVALUATION FOR AD7725 |
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REV. A
AD7725
–11–
Pin No.
Mnemonic S/P
Description
27
STBY
Standby, Logic Input. When STBY is taken high, the device will enter a low power mode.
If the device was fully configured before entering this mode, it will not lose its configuration data.
When STBY is brought low, the device exits the low power mode. If the device
was partially configured before entering the low power mode, it will restart the configuration
process in the case of boot from ROM (BFR) mode, DSP mode, and EPROM mode or, in
parallel mode, a new configure instruction must be issued to configure the device. If the device
was fully configured before entering the low power mode, it will continue to output conversion
results in all serial modes; in parallel mode, the device will wait for an instruction to begin
converting. In STBY mode, the clock input must be continual.
28
DGND
Ground Reference for Digital Circuitry.
29
SYNC
Synchronization Logic Input. When using more than one AD7725 operated from a
common master clock, SYNC allows each ADC to simultaneously sample its analog input
and update its output register. When SYNC is high, the digital filter sequencer counter is
reset to zero and the postprocessor core is reset. Because the digital filter and sequencer
are completely reset during this action, SYNC pulses cannot be applied continuously.
When SYNC is taken low, normal conversions continue, with valid data resulting after the
filter setting time.
30
SOE/CS
Serial Mode.
SOE–Serial Output Enable. In EPROM mode, SOE going low enables the
external EPROM and is used to reset the EPROM’s address counter. In DSP mode,
SOE is an
active high interrupt. It goes high after a power-on reset and after a pulse on the
RESETCFG
pin, indicating the device is ready to be configured. It also goes high following a successful
configuration, indicating that the device was configured correctly.
SOE is reset low when FSI
is detected high by CLKIN. In BFR mode,
SOE pulses high for eight CLKIN cycles at the end
of a successful configuration.
Parallel Mode.
CS–Chip Select Logic Input. This is an active low logic input used in
conjunction with the RD/
WR input to read data from or write data to the device. For a
read operation, the falling edge of
CS takes the bus out of three-state and either the
conversion data or the status register data (depending on the state of the RS input), is
placed onto the data bus, after the time t
31. For a write operation, the rising edge of CS
is used to latch either the configuration data or the instruction (depending on the state of
the RS input) into the AD7725. In this case, the data should be set up for a time t
25 before
the
CS rising edge.
31
SMODE1/DB15
Serial Mode. SMODE1–Serial Mode Select, Logic Input. This pin selects the serial mode to
be used (see Table IV) and thus informs the device where to download configuration data from
automatically on power up. To change the value on this pin, a full power cycle
needs to be performed.
Parallel Mode. DB15–Data Input/Output Bit (MSB).
32
SMODE0/DB14
Serial Mode. SMODE0–Serial Mode Select, Logic Input. This pin selects the serial mode to
be used (see Table IV) and thus informs the device where to download configuration data
from automatically on power-up. To change the value on this pin, a full power cycle needs to
be performed.
Parallel Mode. DB14–Data Input/Output Bit.
33
SCR/DB13
Serial Mode. SCR–Serial Clock Rate Select, Logic Input. With SCR set to logic low,
the serial clock output frequency, SCO, is equal to the CLKIN frequency. A logic high
sets the frequency of SCO to one half the CLKIN frequency.
Parallel Mode. DB13–Data Input/Output Bit.
34
CFGEND/DB12
Serial Mode. CFGEND–Configuration End, Logic Output. A logic high on CFGEND
indicates that device programming is complete and no programming errors occurred.
Parallel Mode. DB12–Data Input/Output Bit.
35
DGND/DB11
Serial Mode. DGND–Digital Ground.
Parallel Mode. DB11–Data Input/Output Bit.
36
DGND/DB10
Serial Mode. DGND–Digital Ground.
Parallel Mode. DB10–Data Input/Output Bit.
37
FSO/DB9
Serial Mode. FSO–Frame Synchronization Output. FSO indicates the beginning of a
word transmission on the SDO pin. The FSO signal is a positive pulse approximately
one SCO period wide.
Parallel Mode. DB9–Data Input/Output Bit.
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