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參數(shù)資料
| 型號(hào)： | AD7725BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT PROG 44MQFP |
| 產(chǎn)品變化通告： | AD7725BSZ Discontinuation 16/Mar/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 900k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 配用： | EVAL-AD7725CBZ-ND - BOARD EVALUATION FOR AD7725 |
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REV. A
AD7725
–21–
Figures 23 and 24 show plots of filter taps and CLKIN
frequency versus IDD.
CLKIN – MHz
180
140
0
14.4
I DD
–
mA
100
40
2.4
4.8
7.2
9.6
12.0
120
60
20
160
80
MAXIMUM IDD
72 TAPS
54 TAPS
HALF_PWR DISABLED
HALF_PWR ENABLED
90 TAPS
108 TAPS
36 TAPS
Figure 23. Typical IDD vs. CLKIN for Various
Numbers of Filter Taps
To get a more accurate number of taps for a given CLKIN
frequency, see Figure 24.
FILTER TAPS
180
140
0
100
10
I DD
–
mA
100
40
20
30
40
50
60
70
80
90
120
60
20
160
80
MAXIMUM IDD
14.4MHz
12MHz
9.6MHz
7.2MHz
4.8MHz
2.4MHz
1MHz
110
Figure 24. Typical IDD vs. Filter Taps for Various
CLKIN Frequencies
Figures 23 and 24 were created for a one-stage low-pass FIR
filter, which will give the worst case IDD figures.
The IDD will decrease as the amount of decimation employed in
the filter is increased.
MODES OF OPERATION
The AD7725 can operate with either a serial or a parallel interface.
These modes are chosen by setting the logic state of the S/
P pin.
PARALLEL MODE
The parallel mode is selected by tying S/
P to DGND. Pro-
gramming the postprocessor and operation of the AD7725 in
parallel mode requires the use of an instruction set. The user
also has access to an on-chip status register that provides infor-
mation about the operation of the device. The parallel interface
is a standard interface that interfaces to digital signal processors
and microprocessors. Figure 25 shows the interface between the
AD7725 and a DSP/microprocessor, and Figures 6, 7, and 8
show the timing of the parallel interface.
AD7725
S/
P
SYNC
RS
CS
RD/
WR
DATA[15:0]
DVAL/INT
DSP/ P
ADDR
RD
DATA[15:0]
INTERRUPT
ADDR
DECODER
WR
Figure 25. AD7725 Parallel Interface to Microprocessor
Operating the AD7725 in Parallel Mode
The AD7725 uses an instruction set, its interrupt pin output
(the INT pin), and an on-chip status register to communicate
with the DSP/microprocessor. An interrupt is issued by the
AD7725 whenever user intervention is required. The interrupt
can be cleared by either writing an instruction or reading the
status register. At the completion of power-on reset, the
AD7725 will issue an interrupt to indicate that user intervention
is required for it to begin communicating with the DSP/micro-
processor. An instruction should then be issued to load the
configuration data to program the postprocessor. Once the
configuration file has been loaded, another interrupt is issued by
the device. The status register can then be read to check if any
errors occurred during configuration. If no errors occur during
the configuration process, an instruction can be issued to inform
the device to begin converting.
Pins RD/
WR, CS, and RS are used along with the data pins D0
to D15 to write instructions/configuration data and read the
status register/conversion data.
During a read cycle, the RS pin informs the AD7725 whether
the status register or a conversion result is being read. When RS
is high, the status register is read while the data register, such as
the device ID or a conversion result, is read when RS is low.
Similarly, during a
WR cycle, an instruction is written when RS
is high and data (such as configuration data) is written when RS
is low (see Table I).
Table I. Reading and Writing
RD/
WR (Pin 7)
RS (Pin 4)
Operation
00
Write Data
01
Write Instruction
10
Read Data
11
Read Status Register
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