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參數(shù)資料
| 型號： | AD7298-1BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SPI/SRL 8CH 20LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 23mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應商設(shè)備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
| 其它名稱： | AD7298-1BCPZ-RLDKR |
AD7298-1
Rev. A | Page 16 of 24
MODES OF OPERATION
The AD7298-1 offers different modes of operation that are
designed to provide additional flexibility for the user. These
options can be chosen by programming the content of the
control register to select the desired mode.
TRADITIONAL MULTICHANNEL MODE OF
OPERATION
The AD7298-1 can operate as a traditional multichannel ADC,
where each serial transfer selects the next channel for conversion.
One must write to the control register to configure and select
the desired input channel prior to initiating any conversions. In
the traditional mode of operation, the CS signal is used to frame
the first write to the converter on the DIN pin. In this mode of
operation, the REPEAT bit in the control register is set to a low
logic level (0), therefore the REPEAT function is not in use. The
data, which appears on the DOUT pin during the initial write to
the control register, is invalid. The first CS falling edge initiates a
write to the control register to configure the device; a conversion is
then initiated for the selected analog input channel (VIN0) on the
subsequent (second) CS falling edge; and the third CS falling edge
will have the result (VIN2) available for reading. The AD7298-1
operates with one cycle latency, therefore the conversion result
corresponding to each conversion is available one serial read
cycle after the cycle in which the conversion was initiated.
As the device operates with one cycle latency, the control
register configuration sets up the configuration for the next
conversion, which is initiated on the next CS falling edge, but
the first bit of the corresponding result is not clocked out until
the subsequent falling CS edge, as shown in Figure 23.
If more than one channel is selected in the control register, the
AD7298-1 converts all selected channels sequentially in ascending
order on successive CS falling edges. Once all the selected channels
in the control register are converted, the AD7298-1 ceases converting
until the user rewrites to the control register to select the next
channel for conversion. This operation is shown in Figure 24.
DOUT returns all 1s if the sequence of conversions is completed or
if no channel is selected.
CS
SCLK
DOUT
DIN
1
10
16
1
16
1
16
1
16
CONVERSION RESULT
FOR CHANNEL 4
CONVERSION RESULT
FOR CHANNEL 1
INVALID DATA
DATA WRITTEN TO CONTROL
REGISTER CHANNEL 4 SELECTED
DATA WRITTEN TO CONTROL
REGISTER CHANNEL 1 SELECTED
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
09321-
009
Figure 23. Configuring a Conversion and Read with the AD7298-1, One Channel Selected for Conversion
CS
SCLK
DOUT
DIN
1
10
16
1
16
1
16
CONVERSION RESULT
FOR CHANNEL 1
CONVERSION RESULT
FOR CHANNEL 5
CONVERSION RESULT
FOR CHANNEL 2
INVALID DATA
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
NO WRITE TO THE
CONTROL REGISTER
DATA WRITTEN TO CONTROL
REGISTER CH 1 AND 2 SELECTED
CS
SCLK
DOUT
DIN
1
16
1
16
DATA WRITTEN TO CONTROL
REGISTER CHANNEL 5 SELECTED
09321-
010
Figure 24. Configuring a Conversion and Read with the AD7298-1, Numerous Channels Selected for Conversion
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