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參數(shù)資料
| 型號： | AD7298-1BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SPI/SRL 8CH 20LFCSP |
| 標準包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 23mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 20-LFCSP-WQ（4x4） |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 8 個單端，單極 |
| 其它名稱： | AD7298-1BCPZ-RLDKR |
AD7298-1
Rev. A | Page 20 of 24
SERIAL INTERFACE
Figure 28 shows the detailed timing diagram for the serial interface
to the AD7298-1. The serial clock provides the conversion clock
and controls the transfer of information to and from the AD7298-1
during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track-and-hold into hold mode
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires 16 SCLK cycles to complete. The track-and-hold
goes back into track mode on the 14th SCLK falling edge as shown
rising edge of CS, the DOUT line goes back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion is terminated, the DOUT line goes back into
three-state, and the control register is not updated; otherwise,
DOUT returns to three-state on the 16th SCLK falling edge.
Sixteen serial clock cycles are required to perform the conversion
process and to access data from the AD7298-1.
For the AD7298-1, four channel address bits (ADD3 to ADD0)
that identify which channel the conversion result corresponds
to, precede the 10 bits of data (see Table 8).
When CS goes low, it provides the first address bit to be read in
by the microcontroller or DSP. The remaining data is then clocked
out by subsequent SCLK falling edges, beginning with a second
address bit. Thus, the first falling clock edge on the serial clock
has the first address bit provided for reading and also clocks out
the second address bit. The three remaining address bits and 12
data bits are clocked out by subsequent SCLK falling edges. The
final bit in the data transfer is valid for reading on the 16th falling
edge having been clocked out on the previous (15th) falling edge.
In applications with a slower SCLK, it may be possible to read in
data on each SCLK rising edge depending on the SCLK frequency.
The first rising edge of SCLK after the CS falling edge would
have the first address bit provided, and the 15th rising SCLK
edge would have last data bit provided.
Writing information to the control register takes place on the
first 16 falling edges of SCLK in a data transfer, assuming the
MSB (that is, the WRITE bit) has been set to 1. The 16-bit word
read from the AD7298-1 always contains four channel address
bits that the conversion result corresponds to, followed by the
12-bit conversion result.
CS
DOUT
DIN
t2
t3
t9
t10
t4
t7
tACQUISITION
t8
tQUIET
t5
t6
SCLK
THREE-
STATE
THREE-
STATE
ADD3
WRITE
REPEAT
CH0
CH1
CH2
CH3
EXT_REF
PPD
DONTC
ADD2
1
2
3
4
5
13
14
B
15
16
ADD1
ADD0
DB9
DB8
DB0
DON’T
CARE
DON’T
CARE
09321-
014
Figure 28. Serial Interface Timing Diagram
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