參數(shù)資料
型號(hào)： AD7298-1BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/25頁(yè)
文件大小： 0K
描述： IC ADC 10BIT SPI/SRL 8CH 20LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 23mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-WQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極
其它名稱(chēng)： AD7298-1BCPZ-RLDKR
AD7298-1
Rev. A | Page 18 of 24
POWER-DOWN MODES
The AD7298-1 has a number of power conservation modes of
operation that are designed to provide flexible power management
options. These options can be chosen to optimize the power
dissipation/throughput rate ratio for different application
requirements. The power-down modes of operation of the
AD7298-1 are controlled by the power-down (PPD) bit in the
control register and the PD/RST pin on the device. When power
supplies are first applied to the AD7298-1, care should be taken
to ensure that the part is placed in the required mode of operation.
Normal Mode
Normal mode is intended for the fastest throughput rate
performance because the user does not have to be concerned
about any power-up times since the AD7298-1 remains fully
powered on at all times. Figure 26 shows the general diagram
of the normal mode operation of the AD7298-1. The conversion
is initiated on the falling edge of CS and the track-and-hold enters
hold mode. On the 14th SCLK falling edge, the track-and-hold
returns to track mode and starts acquiring the analog input, as
described in the Serial Interface section. The data presented to
the AD7298-1 on the DIN line during the first 16 clock cycles of
the data transfer are loaded into the control register (provided the
WRITE bit is 1). The part remains fully powered up in normal
mode at the end of the conversion as long as the PPD bit is set
to 0 in the write transfer during that conversion.
To ensure continued operation in normal mode, the PPD bit
should be loaded with 0 on every data write operation. Sixteen
serial clock cycles are required to complete the conversion and
access the conversion result. For specified performance, the
throughput rate should not exceed 1 MSPS. When a conversion
is complete and the CS has returned high, a minimum of the quiet
time, tQUIET, must elapse before bringing CS low again to initiate
another conversion and access the previous conversion result.
CS
SCLK
DOUT
DIN
1
16
DATA WRITTEN TO CONTROL
REGISTER IF REQUIRED
4 CHANNEL ADDRESS BITS
+ CONVERSION RESULT
09321-
012
Figure 26. Normal Mode Operation
Partial Power-Down Mode
In this mode, part of the internal circuitry on the AD7298-1
is powered down. The AD7298-1 enters partial power-down
on the CS rising edge once the current serial write operation
containing 16 SCLK clock cycles is completed. To enter partial
power-down, the PPD bit in the control register should be set to
1 on the last required read transfer from the AD7298-1. Once in
partial power-down mode, the AD7298-1 transmits all 1s on the
DOUT pin if CS is toggled low.
The AD7298-1 remains in partial power-down until the power-
down bit, PPD, in the control register is changed to Logic Level 0.
The AD7298-1 begins powering up on the rising edge of CS
following the write to the control register disabling the power-
down bit. Once tQUIET has elapsed, a full 16 SCLK writes to the
control register must be completed to update its content with
the desired channel configuration for the subsequent conversion.
A valid conversion is then initiated on the next CS falling edge.
Because the AD7298-1 has one cycle latency, the first conversion
result after exiting partial power-down mode is available in the
fourth serial transfer, as shown in Figure 27. The first cycle updates
the PPD bit, the second cycle updates the configuration and
Channel ID bits, the third completes the conversion, and the
fourth accesses the DOUT valid result. The use of this mode
enables a reduction in the overall power consumption of the device.
Full Power-Down Mode
In this mode, all internal circuitry on the AD7298-1 is powered
down, and no information is retained in the control register or any
other internal register.
The AD7298-1 is placed into full power-down mode by bringing
the logic level on the PD/RST pin low for greater than 100 ns.
When placing the AD7298-1 in full power-down mode, the ADC
inputs must return to 0 V. The PD/RST pin is asynchronous to the
clock; therefore, it can be triggered at any time. The part can be
powered up for normal operation by bringing the PD/RST pin
logic level back to a high logic state.
The full power-down feature can be used to reduce the average
power consumed by the AD7298-1 when operating at lower
throughput rates. The user should ensure that tPOWER-UP has
elapsed prior to programming the control register and initiating
a valid conversion.
CS
SCLK
DOUT
DIN
1
10
16
1
16
1
16
INVALID DATA
WRITE TO THE CONTROL
REGISTER, SELECT CH1, PPD = 0
PART IS IN
PARTIAL
POWER DOWN
WRITE TO CONTROL
REGISTER, PPD = 0.
CONTROL REGISTER CONFIGURED
TO POWER UP DEVICE.
SELECT ANALOG INPUT CHANNELS
FOR CONVERSION. THE NEXT CYCLE
WILL CONVERT THE FIRST CHANNEL
PROGRAMMED IN THIS WRITE OPERATION.
PART BEGINS TO
POWER UP ON CS
RISING EDGE.
THE PART IS FULLY
POWERED UP ONCE THE
WRITE TO THE CONTROL
REGISTER IS COMPLETED.
AD7298 CONVERTING CHANNEL 1
NEXT CYCLE HAS CHANNEL 1
RESULT AVAILABLE FOR READING.
tQUIET
09321-
213
NO WRITE TO
CONTROL REGISTER
Figure 27. Partial Power-Down Mode of Operation
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