參數(shù)資料
型號(hào)： AD7298-1BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/25頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT SPI/SRL 8CH 20LFCSP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 10
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 23mW
電壓電源： 單電源
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 20-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 20-LFCSP-WQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 8 個(gè)單端，單極
其它名稱： AD7298-1BCPZ-RLDKR
AD7298-1
Rev. A | Page 12 of 24
TERMINOLOGY
Signal-to-Noise-and-Distortion Ratio (SINAD)
The measured ratio of signal-to-noise and distortion at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-noise-and-distortion ratio for an ideal N-
bit converter with a sine wave input is given by
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Thus, the SINAD is 61.96 dB for an ideal 10-bit converter.
Total Harmonic Distortion (THD)
The ratio of the rms sum of harmonics to the fundamental. For
the AD7298-1, it is defined as
1
2
6
2
5
2
4
2
3
2
log
20
)
dB
(
V
THD
+
=
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through sixth harmonics.
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Typically, the value of this specification
is determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Integral Nonlinearity
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function. The endpoints are
zero scale, a point 1 LSB below the first code transition, and full
scale, a point 1 LSB above the last code transition.
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
The deviation of the first code transition (00…000) to
(00…001) from the ideal—that is, GND1 + 1 LSB.
Offset Error Matching
The difference in offset error between any two channels.
Gain Error
The deviation of the last code transition (111…110) to
(111…111) from the ideal (that is, VREF 1 LSB) after the offset
error has been adjusted out.
Gain Error Matching
The difference in gain error between any two channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of the conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1 LSB, after the end of the conversion.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the input varies from 5 kHz to 25 MHz.
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
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