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參數(shù)資料
| 型號(hào)： | AD7190BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 31/41頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH 24BIT W/PGA 24TSSOP |
| 設(shè)計(jì)資源： | Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102) |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 4.8k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，雙極；4 個(gè)偽差分，雙極 |
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AD7190
Data Sheet
Rev. C | Page 36 of 40
ENABLE PARITY
The AD7190 also has a parity check function on-chip that
detects 1-bit errors in the serial communications between the
ADC and the microprocessor. When the ENPAR bit in the
mode register is set to 1, parity is enabled. The contents of the
status register must be transmitted along with each 24-bit
conversion when the parity function is enabled. To append the
contents of the status register to each conversion read, the
DAT_STA bit in the mode register should be set to 1. For each
conversion read, the parity bit in the status register is
programmed so that the overall number of 1s transmitted in the
24-bit data-word is even. Therefore, for example, if the 24-bit
conversion contains eleven 1s (binary format), the parity bit is
set to 1 so that the total number of 1s in the serial transmission is
even. If the microprocessor receives an odd number of 1s, it
knows that the data received has been corrupted.
The parity function only detects 1-bit errors. For example, two
bits of corrupt data can result in the microprocessor receiving an
even number of 1s. Therefore, an error condition is not detected.
CALIBRATION
The AD7190 provides four calibration modes that can be pro-
grammed via the mode bits in the mode register. These modes
are internal zero-scale calibration, internal full-scale calibration,
system zero-scale calibration, and system full-scale calibration.
A calibration can be performed at any time by setting the MD2
to MD0 bits in the mode register appropriately. A calibration
should be performed when the gain is changed. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The offset calibration coefficient is subtracted from the result
prior to multiplication by the full-scale coefficient.
To start a calibration, write the relevant value to the MD2 to
MD0 bits. The DOUT/RDY pin and the RDY bit in the status
register go high when the calibration is initiated. When the
calibration is complete, the contents of the corresponding
calibration registers are updated, the RDY bit in the status
register is reset, the DOUT/ RDY pin returns low (if CS is low),
and the AD7190 reverts to idle mode.
During an internal zero-scale or full-scale calibration, the res-
pective zero input and full-scale input are automatically connected
internally to the ADC input pins. A system calibration, however,
expects the system zero-scale and system full-scale voltages to
be applied to the ADC pins before initiating the calibration
mode. In this way, errors external to the ADC are removed.
From an operational point of view, treat a calibration like
another ADC conversion. A zero-scale calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the DOUT/RDY pin to determine the end of calibration via a
polling sequence or an interrupt-driven routine.
With chop disabled, both an internal zero-scale calibration and
a system zero-scale calibration require a time equal to the
settling time, tSETTLE, (4/fADC for the sinc4 filter and 3/fADC for the
sinc3 filter).
With chop enabled, an internal zero-scale calibration is not
needed because the ADC itself minimizes the offset continuously.
However, if an internal zero-scale calibration is performed, the
settling time, tSETTLE, (2/fADC) is required to perform the calibra-
tion. Similarly, a system zero-scale calibration requires a time of
tSETTLE to complete.
To perform an internal full-scale calibration, a full-scale input
voltage is automatically connected to the selected analog input
for this calibration. For a gain of 1, the time required for an
internal full-scale calibration is equal to tSETTLE. For higher gains,
the internal full-scale calibration requires a time of 2 × tSETTLE.
A full-scale calibration is recommended each time the gain of a
channel is changed to minimize the full-scale error.
A system full-scale calibration requires a time of tSETTLE. With
chop disabled, the zero-scale calibration (internal or system
zero-scale) should be performed before the system full-scale
calibration is initiated.
An internal zero-scale calibration, system zero-scale calibration
and system full-scale calibration can be performed at any output
data rate. An internal full-scale calibration can be performed at
any output data rate for which the filter word FS[9:0] is divisible
by 16, FS[9:0] being the decimal equivalent of the 10-bit word
written to Bit FS9 to Bit FS0 in the mode register. Therefore,
internal full-scale calibrations can be performed at output data
rates such as 10 Hz or 50 Hz when chop is disabled. Using these
lower output data rates results in better calibration accuracy.
The offset error is, typically, 100 V/gain. If the gain is changed,
it is advisable to perform a calibration. A zero-scale calibration
(an internal zero-scale calibration or system zero-scale
calibration) reduces the offset error to the order of the noise.
The gain error of the AD7190 is factory calibrated at a gain of 1
with a 5 V power supply at ambient temperature. Following this
calibration, the gain error is 0.001%, typically, at 5 V. Table 23
shows the typical uncalibrated gain error for the different gain
settings. An internal full-scale calibration reduces the gain error
to 0.001%, typically, when the gain is equal to 1. For higher
gains, the gain error post internal full-scale calibration is
0.0075%, typically. A system full-sale calibration reduces the
gain error to the order of the noise.
Table 23. Typical Precalibration Gain Error vs. Gain
Gain
Precalibration Gain Error (%)
8
0.11
16
0.20
32
0.23
64
0.29
128
0.39
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| AD7190WBRUZ | 功能描述:24 Bit Analog to Digital Converter 2, 4 Input 1 Sigma-Delta 24-TSSOP 制造商:analog devices inc. 系列:- 包裝:管件 零件狀態(tài):有效 位數(shù):24 采樣率（每秒）:4.8k 輸入數(shù):2，4 輸入類型:差分，個(gè)偽差分 數(shù)據(jù)接口:SPI，DSP 配置:MUX-PGA-ADC 無線電 - S/H:ADC:- A/D 轉(zhuǎn)換器數(shù):1 架構(gòu):三角積分 參考類型:外部， 內(nèi)部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:2.7 V ~ 5.25 V 特性:PGA，溫度傳感器 工作溫度:-40°C ~ 105°C 封裝/外殼:24-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商器件封裝:24-TSSOP 標(biāo)準(zhǔn)包裝:1 |
| AD7190WBRUZ-RL | 制造商:Analog Devices 功能描述: |
| AD7191 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pin-Programmable, Ultralow Noise, 24-Bit, Sigma-Delta ADC for Bridge Sensors |
| AD7191A/0B | 制造商:Sony Nec Optiarc America 功能描述:DOUBLE DUAL INTERNAL DVDRW PATA BEZEL 20X/18X12XRAM - Bulk |
| AD7191BRUZ | 功能描述:IC ADC 2CH 24B SD 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極 |
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