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參數(shù)資料
| 型號： | AD6652PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機(jī) |
| 文件頁數(shù)： | 71/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652PCB |
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AD6652
0x1E: Port Clock Control
Bit 0 determines whether PCLK is supplied externally by the
user or derived internally in the AD6652. If PCLK is derived
internally from CLK (Bit 0 = 1), it is output through the PCLK
pin as a master clock. For most applications, PCLK is provided
by the user as an input to the AD6652 via the PCLK pin.
Rev. 0 | Page 71 of 76
Bits 2 and 1 allow the user to divide CLK by an integer value to
generate PCLK (00 = 1, 01 = 2, 10 = 4, 11 = 8).
MICROPORT CONTROL
The AD6652 has an 8-bit microprocessor port or
microport
. The
microport interface is a multimode interface that is designed to
give flexibility when dealing with the host processor. There are
two modes of bus operation: Intel nonmultiplexed mode (INM),
and Motorola nonmultiplexed mode (MNM). The mode is
selected based on the host processor and which mode is best
suited to that processor. The microport has an 8-bit data bus
(D[7:0]), 3-bit address bus (A[2:0]), 3 control pin lines (CS, DS,
or RD, R/W or WR), and one status pin (DTACK or RDY). The
functionality of the control signals and status line changes
slightly depending upon the mode that is chosen.
Write Sequencing
Writing to an internal location is achieved by first writing the
upper two bits of the address to Bits 1–0 of the ACR (Access
Control Register, External Address 7). Bits 7:2 can be set to
select the channel, as indicated above. The CAR is then written
with the lower eight bits of the internal address (the CAR can be
written before the ACR, as long as both are written before the
internal access). Data Register 2 (DR2) and Data Register 1
(DR1) must be written first, because the write to Data Register
DR0 triggers the internal access. Data Register DR0 must always
be the last register written to initiate the internal write.
Read Sequencing
Reading from the microport is accomplished in the same
manner. The internal address is set up the same way as the
write. A read from Data Register DR0 activates the internal
read; thus, Register DR0 must always be read first to initiate an
internal read followed by DR1and DR2. This provides the
8 LSBs of the internal read through the microport (D[7:0]).
Additional data registers can be read to read the balance of the
internal memory.
Read/Write Chaining
The microport of the AD6652 allows for multiple accesses while
CS is held low. (CS can be tied permanently low, if the micro-
port is not shared with additional devices.) The user can access
multiple locations by pulsing the WR or RD line and changing
the contents of the external 3-bit address bus. External access to
the external registers of Table 22 is accomplished in one of two
modes using the CS, RD, WR, and MODE inputs. The access
modes are Intel nonmultiplexed mode and Motorola nonmulti-
plexed mode. These modes are controlled by the MODE input
(MODE = 0 for INM, MODE = 1 for MNM). CS, RD, and WR
control the access type for each mode.
Intel Nonmultiplexed Mode (INM)
MODE must be tied low to operate the AD6652 microprocessor
in INM mode. The access type is controlled by the user with the
CS, RD (DS), and WR (R/W) inputs. The RDY (DTACK) signal
is produced by the microport to communicate to the user that
an access has been completed. RDY (DTACK) goes low at the
start of the access and is released when the internal cycle is
complete. See the timing diagrams for both the read and write
modes in the DDC Timing Diagrams section.
Motorola Nonmultiplexed Mode (MNM)
MODE must be tied high to operate the AD6652 microproces-
sor in MNM mode. The access type is controlled by the user
with the CS, DS (RD), and R/W (WR) inputs. The DTACK
(RDY) signal is produced by the microport to communicate to
the user that an access has been completed. DTACK (RDY) goes
low when an internal access is complete and then returns high
after DS (RD) is deasserted. See the timing diagrams for both
the read and write modes in the DDC Timing Diagrams
section.
Microport Programming Overview
The AD6652 uses an indirect addressing scheme. The external
memory map (or external registers) is used to access the
internal memory maps that are made up of a channel memory
map and an output port memory map. The 4-channel memory
pages are decoded using A[9:8] given in the External Memory
Register 7 of the access control register (ACR). The output port
register memory map is selected using Bit 5 of External
Address 3 (sleep register). When this bit is written with a 0, the
channel memory map is selected; when this bit is 1, the output
port memory map is selected.
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