參數(shù)資料
型號： AD6652PCB
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： 12位，65 MSPS的IF到基帶分集接收機
文件頁數(shù)： 63/76頁
文件大?。?/td> 1839K
代理商： AD6652PCB
AD6652
INPUT PORT CONTROL REGISTERS
The i
eat
rimarily for level con
f
m
m
s
usin
lo
LIA,
, LIB, and LIB pins.
Rev. 0 | Page 63 of 76
t po
ble variou
trol. Dep
late
ures used p
ode of operation, up to four different signal paths can be
onitored with these registers. These features are accessed by
etting Bit 5 of External Address 3 (sleep regi
g the CAR (External Address 6) to address the eight
cations ava lable. Response to these settings is directed to
LIA
g on the
nd then
npu
rt control registers ena
s i
ndin
e
nput-re
d
ster) a
the
To access the input port registers, the progra gain contro
ld be wr ten high. The CAR is then wri en with the
ess to th
orrect input port register.
addr
e c
0x00: Lower Threshold A
This w
m
eq
v
n
o
in
r
0x01: Upper Threshold A
This w
m
eq
v
n
o
or
) to become active.
0x02: Dwell Time A
T
the lo
reshold before the LI pin i
inpu
etector to work, the dw
leas
to 0, the LI function
regi
en the lower thresh
exc
to the upper threshold
load
begins to count high speed clo
th
incr
ove the lower threshold, the
wait
signal to fall below the l
0x03: Ga
B
in
lear, then t
LI signal is high when the up
een exceed
. However, if this bit is set, the LI pin is low
hen active. his allows maximum flexibility
is function
th
.
ord is 10 bits wide and maps to the 10 MSB of the
antissa. If the upper 10 bits of Input Port A are less than o
ual to this alue, then the lower threshold
ormal chip peration, this starts the dwell time counter. If he
put signal increases above this value, then t e counter is
eloaded an awaits the input to drop back t
s been met. I
ha
his level.
ord is 10 bits wide and maps to the 10 MSB of the
antissa. If t e upper 10 bits of Input Port A re greater th
ual to this alue, then the upper threshold as been met.
ormal chip peration, this causes the apprpr
LIA
r
m
tt
l bit
shou
o t
a
h
an o
In
his word sets the time that the input signal must be at or
wer th
t level d
t 1. If set
ster. Wh
ursion in
ed and
e input is a or below the lower threshold. I
eases ab
s for the
in Range A Control Register
it 4 determ es the polarity of LIA and LIA
he
ed
w
T
w
s deac
ell time m t be set to a
s are disable
old is met fol
, the dwel
ck
cy
f th
ed. For the
tivat
us
d. T
low
l tim
his is a 20
ing an
e counter i
cles as long
e signal
eloaded
old again.
h
res
coun
er th
belo
t
-bit
s
as
ow
ter is r
and
. If this bit is
r threshold has
pe
hen using
it 3 = 0 (Re
B
ved).
Bit 2–0 determines the internal latency of the gain detect
function. When the LIA, LIA
used to change an attenuator or gain stage. Because
DC, there is a latency associated with the
A
e settling of the gain change. This register
a
delay of the LIA, LIA
llows the internal
p
wer Threshold B
is 10 bits wide and maps to the 10 MSB of the
er 10 bits of Input Port B are less than or
e
e, then the lower threshold has been met. In
n
peration, this starts the dwell time counter. If the
al increases above this value, then the counter is
aits the input to drop back to this level.
0x05: Upper Threshold B
This w rd is 10 bits wide and maps to the 10 MSB of the
m
. If the upper 10 bits of Input Port B are greater than or
e
is value, then the upper threshold has been met. In
n
ip operation, this causes the appropriate LI pin (LIB
or
LIB
) to become active
0x06: Dwell Time B
d sets the time that the input signal must be at or below
t
i
e dwell time must be set to at
1. If set to 0, the LI functions are disabled. This is a 20-bit
. When the lower threshold is met following an
into the upper threshold, the dwell time counter is
aded and begins to count high speed clock cycles as long as
is at or below the lower threshold. If the signal
the input
increases above the lower threshold, the counter is relo
waits for t
0x0: G
Bit 4 determines th
h when the upper threshold has
, if this bit is set, the LI pin is low
is allows maximum flexibility when using
when active. Th
this function.
c
b
w
ser
pins are made active, they are
typically
this is prior to the A
DC and with th
signal to be
rogrammed.
0x04: Lo
This word
mantissa. If the upp
qual to this valu
ormal chip o
input sign
reloaded and aw
antissa
qual to th
ormal ch
pin is deactivated. For the
aded and
he signal to fall below the lower threshold again.
ain Range B Control Register
e polarity of LIB and LIB
clear, then the LI signal is hig
However
been exceeded.
This wor
he lower threshold before the LI
nput level detector to work, th
least
register
excursion
lo
. If this bit is
B
(Reserved.
B
f
t
t
t
register a
b
e programmed.
etermines the internal latency of the gain detect
. When the LIB, LIB
unction
pins are made active, they are
sed to change an attenuator or gain stage. Because
r to the ADC, there is a latency associated with
nd with the settling of the gain change. This
llows the internal delay of the LIB, LIB
it 3 = 0
it 2–0 d
ypically u
his is prio
he ADC a
signal to
相關(guān)PDF資料
PDF描述
AD6816 Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片)
AD693(中文) Loop-Powered 4-20 mA Sensor Transmitter(環(huán)路供電,4-20mA傳感器變送器)
AD7010ARS MIL-spec connector accessory
AD7010 CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口)
AD7011 CMOS, ADC p/4 DQPSK Baseband Transmit Port
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6652XBC 制造商:Analog Devices 功能描述:- Bulk
AD6653 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver
AD6653-125EBZ 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653
AD6653-150EBZ 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk
AD6653BCPZ-125 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*