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參數(shù)資料
| 型號： | AD6652PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 44/76頁 |
| 文件大小： | 1839K |
| 代理商： | AD6652PCB |
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AD6652
for averaging and decimating the update samples and taking
their square root to f
mode. In place of the request
de
ipping level is subtracted, leaving an error term to be proc-
der loop filter. The rest of the loop
s the desired signal level mode. This
operates the same way a
way, the truncation error is calculated and the AGC loop
operates to maintain a constant truncation error level.
Rev. 0 | Page 44 of 76
vel
recei
aver
average power for AGC error calculation and loop filtering. This
ext rnal signal synchronizes the AGC changes to the Rake
iver and makes sure that the AGC gain word does not
ge over a symbol period and, therefore, mor
esti ation. The external synchronization signal is connected t
one or more of the pin sync pins (A, B, C, or D).
he
e AD6652 to update the
rece
chan
e accurate
m
o
Pin
coun
the u
the u
chos
AGC B shares the pin synch that the user has assigned to DDC
processing Channel 2. Therefore, the user must attach the
external sync signal to the pin sync that will be assigned to
DDC Channel 2.
at
e,
hannel 0. Likewise, the hold-off counter of
and
number that corresponds to the number of CLK cycles that will
be counted ( a known delay) before a new C
is updated. Writing a logic high to
IC decimated value
the proper pin sync pin
triggers the AGC hold-off counter with a one-shot pulse every
time the pin is written high. Once triggered, the counter counts
down to a value of one and then causes a start of decimation for
w update sample.
a ne
Note
counter. Setting the hold-off count to one provides the smallest
y.
he hold-off
dela
If the user chooses not to use pin sync signals, the user can use
S
cont
0x12
n written high, performs an immediate start of
date sample. This bit has a one-shot
ristic an
ot need
w logic hi
being writte
passes the AG hold-off coun
ctions witho
elay.
fun
ut d
to respond
it. Use of the sync now bit
s and performs sync
ter
ch
Pin Sync logic high
initiates a new trigger event for the
Ea
hold-off counter unless
First Sync Only
of the AGC’s control
register (Bit 1) is set to logic high. When high, only the first sync
signal is recognized and any others disregarded until
First Sync
Only
is reset.
een reserved for configuring
ind rms samples, as in desired signal level
sired signal level, a desired
cl
essed by the second-or
Apart from Bit 4 of the AGC control words, the only register
setting changes compared to the desired signal level mode is
that the desired clipping level is stored in the AGC desired le
registers (0x0C, 0x15) instead of the request signal level (as in
desired signal level mode).
SYNCHRONIZATION
In i stances where the AGC output is connected to a Rake
ver, a signal from the Rake receiver can synchronize t
age-and-update section of th
synchronization requires the use of an AGC hold-off
ter. The hold-off counter of AGC A shares the pin sync th
ser has assigned to DDC processing Channel 0. Therefor
ser must attach the external sync signal to the pin sync
en for DDC C
The hold-off counter register, 0x0B and 0x13 for AGC A
AGC B, respectively, must be programmed with a 16-bit
: Setting the hold-off count to zero disables t
the
ync Now
command through the microport. Each AGC
rol register has a sync now bit in Registers 0x0A:3 and
:3 that, whe
decimation for a new up
characte
d does n
to a ne
gh
by
C
to be reset in order
n to
Along with updating a new decimation value, the CIC filter
accumulator can be reset if the
Init on Sync
bit (Bit 2) of the
AGC control register is set.
Init on Sync
is triggered by either
sync signal, pin sync, or sync now.
Addresses 0x0A to 0x11 have b
AGC A, and Addresses 0x12 to 0x19 have been reserved for
configuring AGC B. The register specifications are detailed in
Table 29.
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