- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375235 > AD6652PCB (Analog Devices, Inc.) 12-Bit, 65 MSPS IF to Baseband Diversity Receiver PDF資料下載
參數(shù)資料
| 型號： | AD6652PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 53/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652PCB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
AD6652
LINK PORT
The AD6652 has two configurable link ports that provide a
seamless data interface with the TigerSHARC TS-101 series
DSP. Each link port allows the AD6652 to write output data to
the receive DMA channel in the TigerSHARC for transfer to
memory. Because they operate independently o
each link port can be connected to a different TigerSHARC or
different link ports on the same TigerSHARC. Figure 59 sh
how to connect one of the two AD6652 link ports to one of the
four TigerSHARC link ports. Link Port A is configured thro
Register 0x1B and Link Port B is configured through
Rev. 0 | Page 53 of 76
f each other,
ows
ugh
Register 0x1D.
AD6652
LCLKIN
LCLKOUT
LDAT
PCLK
TigerSHARC
LCLKIN
LCLKOUT
LDAT
PCLK
8
0
Figure 59. Link Port Connection between AD6652 and TigerSHARC
LINK PORT DATA FORMAT
Each link port can output data to the TigerSHARC in five
different formats: 2-channel, 4-channel, dedicated AGC,
redundant AGC with receive signal strength indicator (RSSI)
word, and redundant AGC without RSSI word. Each format
outputs two bytes of I data and two bytes of Q data to form a
4-byte IQ pair. Because the TigerSHARC link port transfers data
in quad-word (16-byte) blocks, four IQ pairs can make up one
quad-word. If the channel data is selected (Bit 0 = 0 of 0x1B/
0x1D), then 4-byte IQ words of the four channels can be outpu
in succession, or alternating channel pair IQ
output. Figure 60 and Figure 61 show the quad-word trans-
mitted for each case with corresponding register values for
configuring each link port.
t
words can be
LINK PORT
A OR B
CH 0 I, Q
(4 BYTES)
CH 1 I, Q
(4 BYTES)
CH 2 I, Q
(4 BYTES)
CH 3 I, Q
(4 BYTES)
ADDR 0x1B OR 0x1D BIT 0 =
C
(4
CH 0 I, Q
(4 BYTES)
0, BIT 1 = 0
BYTES)
CH 1 I, Q
(4 BYTES)
RT B
C
(4
, Q
)
0
om RCF
utput
t with th
ured to o
t data fro
e same d
rds (Bit 2
two bytes (12 bits appended with 4 0s), so the link port sends
two bytes of 0s immediately after each RSSI wor
d to make a full
16-byte quad-word.
LINK PORT A
H 0 I, Q
BYTES)
CH 1 I, Q
(4
LINK PO
H 2 I, Q
BYTES)
CH 3 I, Q
(4 BYTES)
CH 2 I, Q
(4 BYTES)
CH 3 I
(4 BYTES
ADDR 0x1B AND 0x1D BIT 0 = 0, BIT 1 = 1
Figure 60. Link Port Data fr
If AGC o
be sen
config
outpu
ting th
IQ wo
is selected (Bit 0 = 1), then RSSI information can
e IQ pair from each AGC. Each link port can be
utput data from one AGC, or both link ports can
m the same AGC. If both link ports are transmit-
ata, then RSSI information must be sent with the
= 0). Note that the actual RSSI word is only
Note that Bit 0 = 1, Bit 1 = 0, and Bit 2 = 1 is not a valid
configuration. Bit 2 must be set to 0, to output AGC A IQ and
RSSI words on Link Port A and AGC B IQ and RSSI words on
Link Port B.
LINK PORT
A OR B
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 0
LINK PORT
A OR B
ADDR 0x1B OR 0x1D BIT 0 = 1, BIT 1 = 0, BIT 2 = 1
LINK PORT A
LINK PORT B
ADDR 0x1B AND 0x1D BIT 0 = 1, BIT 1 = 1, BIT 2 = 0
AGC A I, Q
(4 BYTES)
AGC A RSSI
(4 BYTES)
AGC A I, Q
(4 BYTES)
AGC A RSSI
(4 BYTES)
AGC B I, Q
(4 BYTES)
AGC B RSSI
(4 BYTES)
AGC B I, Q
(4 BYTES)
AGC B RSSI
(4 BYTES)
AGC A I, Q
(4 BYTES)
AGC B I, Q
(4 BYTES)
AGC A I, Q
(4 BYTES)
AGC B I, Q
(4 BYTES)
, Q
AGC B RSSI
(4 BYTES)
0
Figure 61. Link Port Data from AGC
ng from the AD6652. PCLK can be run as fast
as 100 MHz in slave mode.
lete
transmission of the full 16 bytes of a TigerSHARC quad-word.
st
o
he
nd has
he
RC.
AGC A I, Q
(4 BYTES)
AGC A RSSI
(4 BYTES)
AGC B I
(4 BYTES)
LINK PORT TIMING
Both link ports run off of PCLK, which can be externally
provided to the chip (Address 0x1E Bit 0 = 0) or generated from
the master clock of the AD6652 (Address 0x1E Bit 0 = 1). This
register boots to 0 (slave mode) and allows the user to control
the data rate comi
The link port provides 1-byte data words (LA[7:0], LB[7:0]
pins) and output clocks (LACLKOUT, LBCLKOUT pins) in
response to a ready signal (LACLKIN, LBCLKIN pins) from the
receiver. Each link port transmits 8 bits on each edge of
LCLKOUT, requiring 8 LCLKOUT cycles to comp
Due to the TigerSHARC link port protocol, the AD6652 mu
wait at least 6 PCLK cycles after the TigerSHARC is ready t
receive data, as indicated by the TigerSHARC setting t
respective AD6652 LCLKIN pin high. Once the AD6652 link
port has waited the appropriate number of PCLK cycles a
begun transmitting data, the TigerSHARC does a connectivity
check by sending the AD6652 LCLKIN low and then high while
the data is being transmitted. This tells the AD6652 link port
that the TigerSHARC’s DMA is ready to receive the next quad-
word after completion of the current quad-word. Because t
connectivity check is done in parallel to the data transmission,
the AD6652 can stream uninterrupted data to the TigerSHA
D0 D1 D2 D3
D4
D15 D0 D1 D2
NEXT QUAD-WORD
TigerSHARC READY TO
RECEIVE QUAD-WORD
WAIT
≥
6 CYCLES
LCLKIN
TigerSHARC READY TO
RECEIVE NEXT QUAD-WORD
LCLKOUT
LDAT[7:0]
0
0
Figure 62. Link Port Data Transfer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6816 | Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) |
| AD693(中文) | Loop-Powered 4-20 mA Sensor Transmitter(環(huán)路供電,4-20mA傳感器變送器) |
| AD7010ARS | MIL-spec connector accessory |
| AD7010 | CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口) |
| AD7011 | CMOS, ADC p/4 DQPSK Baseband Transmit Port |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6652XBC | 制造商:Analog Devices 功能描述:- Bulk |
| AD6653 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6653-125EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653 |
| AD6653-150EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk |
| AD6653BCPZ-125 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 |
發(fā)布緊急采購，3分鐘左右您將得到回復。