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參數(shù)資料
| 型號： | AD6652PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 49/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652PCB |
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AD6652
Hop with Pin Sync
Just as
pins, A, B, C, and D, which are used for very accurate channe
synchronization. Each DDC channel can be programmed to
respond to any or all four SYNC pins.
Rev. 0 | Page 49 of 76
in the start function, the AD6652 provides four SYNC
l
rite the NCO frequency hold-off counter(s) (0x84) to the
W
appropriate value (greater than 0 and less than 2 ).
16
he hop on pin sync bit high and the appropriate sync
enable high at External Address 4.
K
c logic high
initiates a new
or the hold-off counter unless
First Sync Only,
trigger event f
External Address 4:6 is set to logic high. When high, only the
first sync signal is recognized and any others are disregarded
until
First Sync Only
is re
channels do not need to be p
frequency hop.
set. Unlike the start function, the
laced in sleep mode to achieve a
r at
a DDC channel by writing to the 0x82 and
t is advantageous to do so in the
0x88:8–7 registers, if i
application.
m when the external signal on the SYNC input pin
goes high to when the NCO begins processing data is equal to
the time period set up by the NCO frequency hold-off counter
(0x84) plus five master clock cycles.
Synchronization of hop with one of the external SYNC pins is
described as follows:
1.
2.
Write the NCO Frequency Register(s), 0x85 and 0x86, to
the new desired frequency.
3.
Set t
pin
4.
Set the sync input select bits
for each active channel
. This is
done at Address 0x88:8–7. The truth table for these bits is
the same as for the start with pin sync, in Table 20.
When the selected sync pin is sampled high by the AD6652
CLK, this enables the count-down of the NCO frequency
hold-off counter. The counter is clocked with the AD6652 CL
signal. When it reaches a count of 1, the new frequency is
loaded into the NCO. Each
Pin Syn
Note: Each channel has a redundant pin-sync control registe
Address 0x82. This register mimics the programming as set in
External Memory Address 4:6–4. The user can control the pin
sync function of
The time fro
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