參數(shù)資料
型號(hào)： AD6652PCB
廠商： Analog Devices, Inc.
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： 12位，65 MSPS的IF到基帶分集接收機(jī)
文件頁(yè)數(shù)： 24/76頁(yè)
文件大小： 1839K
代理商： AD6652PCB
AD6652
THEORY OF OPERATIO
The AD6652 has two analog input channels, four digital filter-
ing channels, and two digital output channels. The IF input
signal passes through several stages before it appears at th
output port(s) as a well-filtered, decimated digital baseba
signal:
Rev. 0 | Page 24 of 76
N
e
nd
n
2× interpolation and channel interleave
ront
CF stages to achieve demanding
filtering objectives that are not possible with just one channel.
In the following sections, each st ge is examined to allow the
user to f
ully utilize the AD6652’s capabilities.
The dual ADC design is useful for diversity reception of signals,
where the ADCs are operating identically on the same carrier
but from two separate antennae. The ADCs can also be
operated with independent analog inputs. The user can sample
any fs/2 frequency segment from dc to 100 MHz using
appropriate low-pass or band-pass filtering at the ADC inputs
with little loss in ADC performance. Operation to 200 MHz
analog input is permitted, but at the expense of increased ADC
distortion.
In nondiversity applications, up to four GSM/EDGE-type
carriers can be concurrently processed from the ADC stage.
Wideband signals, such as WCDMA/CDMA2000, require the
power of two AD6652 processing channels per carrier to
adequately remove adjacent channel interference. When
diversity techniques a
can be processed is halv
ment of diversity reception.
er of carriers that
ocessing require-
ble channel multiplexing in the digital downconverter
DC) stage allows one to four channels to be interleaved onto
ronization input pins allow startup,
one output port. Four synch
frequency hop, and AGC functions to be precisely orchestr
with other devices. The NCO’s phase can be set to produce a
known offset relative to another channel or device.
ated
RE
The AD6652 front-end consists of two high performance, 12-bit
ADCs, preceded by differential sample-and-hold amplifiers
(SHA) that provide excellent SNR performance from dc to
200 MHz. A flexible, integrated voltage reference allows analog
inputs up to 2 V p-p. Each channel is equipped with an
overrange pin that toggles high whenever the analog input
exceeds the upper or lower reference voltage boundary. ADC
outputs are internally routed to the input matrix of the DDC
stage for channel distribution. The ADC data outputs are not
directly accessible to the user.
Each sample-and-hold amplifier (SHA) is followed by a pipe-
lined switched capacitor ADC. The pipelined ADC is divided
into three sections, consisting of a 4-bit first stage followed by
eight 1.5-bit stages and a final 3-bit flash. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 12-bit result in the digital correction logic. The
pipelined architecture permits the first stage to operate on a
new input sample while the remaining stages operate on the
preceding samples. Sampling occurs on the rising edge of the
clock.
Analog Input Operation
The analog inputs to the AD6652 are differential switched
capacitor SHAs that have been designed for optimum perform-
ance while processing differential input signals. The AD6652
accepts inputs over a wide common-mode range; however, an
input common-mode voltage V
CM
, one-half of AVDD, is
recommended to maintain optimal performance and to
minimize signal-dependent errors.
Referring to Figure 38, the clock signal alternatively switches the
SHA between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt capaci-
tors should be removed. In combination with the driving source
impedance, the shunt capacitors would limit the input
bandwidth.
12-bit A/D conversio
Frequency translation from IF to baseband using
quadrature mixers and NCOs
Second-order resampling decimating CIC FIR filter
(rCIC2)
Fifth-order decimating CIC FIR filter (CIC5)
RAM coefficient decimating FIR filter (RCF)
Automatic gain control (AGC)
Any stage can be bypassed with the exception of the ADC f
end. Any combination of processing channels can be combined
or interleaved after the R
re employed, the numb
ed due to the dual pr
Flexi
(D
Programming and control of the AD6652 is accomplished using
an 8-bit parallel interface.
ADC ARCHITECTU
相關(guān)PDF資料
PDF描述
AD6816 Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片)
AD693(中文) Loop-Powered 4-20 mA Sensor Transmitter(環(huán)路供電,4-20mA傳感器變送器)
AD7010ARS MIL-spec connector accessory
AD7010 CMOS JDC DQPSK Baseband Transmit Port(CMOS 基帶傳輸口)
AD7011 CMOS, ADC p/4 DQPSK Baseband Transmit Port
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6652XBC 制造商:Analog Devices 功能描述:- Bulk
AD6653 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver
AD6653-125EBZ 制造商:Analog Devices 功能描述:Evaluation Board For AD6653 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk 制造商:Analog Devices 功能描述:KIT EVALUATION BOARD AD6653
AD6653-150EBZ 制造商:Analog Devices 功能描述:EVAL BD FOR AD6653 - Bulk
AD6653BCPZ-125 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*