參數(shù)資料
型號(hào)： AD6652BBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, BGA-256
文件頁(yè)數(shù)： 58/76頁(yè)
文件大?。?/td> 1839K
代理商： AD6652BBC
AD6652
Rev. 0 | Page 58 of 76
NEL 3
P
2
AP
US
A
R
E
IDDEN BY BROADCAST FEATURE.
0x08
S1
S2
D1
TO
D4
ENB
CHANNEL
CHANNEL
MEMORY MAP
CHANNEL 1
MEMORY M
2
BITS [1:0] OF
ACR,
EXTERNAL
ADDRESS 7
CHANNEL 0
MEMORY MAP
CHAN
MEMORY MA
*CHANNEL DECODER CAN BE
OVERR
OUTPUT PORT
CONTROL
REGISTERS
20
DATA BUS
ENB
DR2, DR1, DR0,
EXTERNAL
ADDRESSES 2, 1, 0
CCESS TO OUTPUT CONTROL
EGISTERS, BIT 5, SLEEP REGISTER,
XTERNAL ADDRESS 3
0x1E
8
CAR, EXTERNAL
ADDRESS 6
0x00
INPUT PORT
CONTROL
REGISTERS
ADDRESS B
A[9:8] FROM
0
Block Diagram of the AD6652 Inte
en
ounter at Address 0x84 is loaded and begins
the hop hold-off c
to count down. When the count reaches a v
channel’s NCO frequency accumu tor is l
from Channel Addresses 0x85 and 0x86. W
written high, the start hold-off counter is loaded with the value
at Address 0x83 and begins to count down. When the count
reaches a value of 1
and the channel is started.
0x82: Pin_SYNC Register
This register m
Address 4. Because t
Address 4 applies to all four chan
particular channel by o
programming provided
user does
alue of 1, the
oaded with the data
hen the
start bit is
la
, the sleep bit in Address 0x80 is written low
imics Bits 4, 5, and 6 of External Memory Map
he programming at External Memory
nels, the user can customize a
verwriting the data in 0x82.If the initial
by External Address 4 is satisfactory, the
not need to reprogram the elements of this register.
the Hop_En or the
atic
standing the Pin_SYNC
lv
s
he 16-bit value
is
n be used in this way to
esolution of the ADC
ck. S
further
ormation ab
itten to Logic
NC pulse arr
es not respond to a SYNC pulse.
0x84: Hop or Frequency Hold-Off Counter
The NCO frequency hold-off counter is loaded with the 16-bit
value written to this address upon receipt of either a Soft_SYNC
or Pin_SYNC. The counter begins counting, and when the
count reaches a value of 1, the 32-bit NCO frequency word is
updated with the values at 0x85 and 0x
hop or Hop_SYNC. Writing this register to a value of 1 causes
the NCO frequency to be updated immediately when the SYNC
comes into the channel. If it is written to a 0, then no Hop
occurs. NCO hops can be either phase-continuous or non-
phase-continuous, depending upon the state of Bit 3 of the
ilter phase adjustment. If this register is
hen the start occurs immediately after the
s. If it is written to Logic 0, then the counter
ive
86. This is known as a
Figure 63.
rnal Memory Maps and Controls
0x81: Soft_SYNC Register
This register is used to initiate software-generated SYNC events
through the microport. It mimics the programming of Bits 4
and 5 at External Address 5. If the hop bit is written high, th
Unlike the two bits in 0x81 above, setting
Start_En (Bits 1 and 0) of this register does
not
trigger anything.
These bits simply allow, or enable, an external synchronizing
signal to be routed to the channel’s start and/or hop multi-
plexers. Even though a signal has been enabled to reach the
multiplexer, it still needs to be selected. This job is accomplished
by Bits 8 and 7 of 0x88, as discussed below. The schem
diagram of Figure 53 is helpful in under
enabling and selection bits of the invo ed registers.
Bit 2 of 0x82 engages the first sync only function for the
channel. This bit is a copy of External Address 4, Bit 6, but can
be overwritten to change the programming of a particular
channel. If this bit is clear, each PIN_SYNC restarts or rehop
the channel. If this bit is set, then only the first sync pulse causes
the action to occur.
0x83: Start Hold-Off Counter
The start hold-off counter is loaded with t
written to this address. When the Start function is triggered by
either a Soft_SYNC or Pin_SYNC, the hold-off counter begins
decrementing. When the count reaches a value of one, the
channel is brought out of sleep mode and begins processing
data.
If the channel is already running, the phase of the filter(s)
adjusted such that multiple AD6652s can be synchronized.
A periodic pulse on the SYNC pin ca
adjust the timing of the filters with the r
sample clo
ee the 0xA1 register description for
inf
out f
wr
1, t
SY
do
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