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參數(shù)資料
| 型號： | AD6652BBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, BGA-256 |
| 文件頁數(shù)： | 47/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BBC |
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AD6652
Rev. 0 | Page 47 of 76
CHANNEL 0
START
SYNC
MULTIPLEXER
CHANNEL 0
HOP
SYNC
HOP EXT ADD 5:5
SOFT SYNC0 EXT ADD 5:0
SELECT LINES
FROM NCO
CONTROL REGISTER
TO START HOLD-OFF COUN
D EXT ADD 4:5
SELECT LINES
FROM NCO
CONTROL REGISTER
TO NCO HOLD-OFF COUNT
0
Note that Multiple Qualifiers Are Required to Enable
to a Hop or Start Hold-Off Counter
MULTIPLEXER
START EXT ADD 5:4
SOFT SYNC0 EXT ADD 5:0
TER
ER
START SYNC ENABLE, 0x82:0 AND EXT ADD 4:4
A
NCB
SYNCC
SYNCD
0x88:8
0x88:7
HOP SYNC ENABLE, 0x82:1 AN
SYNCA
SYNCB
SYNCC
SYNCD
0x88:8
0x88:7
PIN SYNC_EN B*
PIN SYNC_EN C*
PIN SYNC_EN D*
SYNCB PIN
SYNCC PIN
SYNCD PIN
*FROM EXTERNAL MEMORY ADDRESS REGISTER 4:3-0
NOTE: ALL CIRCUITRY AND SIGNALS ARE IDENTICAL AND REPEATED FOR
EACH CHANNEL EXCEPT SOFT SYNCx. SOFT SYNCx CONTROL SIGNALS
ARE ASSIGNED TO A SINGLE CHANNEL AND ARE NOT SHARED WITH ANY
OTHER CHANNEL.
Figure 53. Synchronizing Signal Routing Example, Channel 0 ;
either a Pin_Sync or a Soft_Sync Signal to Be Routed
Start with Soft Sync
The AD6652 includes the ability to synchronize channels or
chips using the microport. One action to synchronize is the
start of channels or chips. The start update hold-off counter
(0x83) in conjunction with the start bit and sync bit (External
Address 5) allows this synchronization. The start update hold-
off counter delays the start of a channel by the 16-bit value
programmed at 0x83 (number of AD6652 CLK periods Use
the following me
thod to synchronize the start of
channels via microprocessor control:
multiple
reset to the
SYNC
SY
PIN SYNC_EN A*
SYNCA PIN
AD6652 HARDWARE AND SOFTWARE SYNC
CONTROL FOR ONE PROCESSING CHANNEL
).
1.
Place the channels in sleep mode (a hard
AD6652 RESET pin forces all four DDC processing
channels into sleep mode).
1. If the chip or channels have not been completely
programmed, write all other registers now.
e clocked
at
ntageous to do so in the application.
The time from when the DTACK
acknowledges t
he receipt of the soft sync command
when the DDC channel begins processing data is equal to the
time period set up by the start hold-off counter value at 0x83
plus six CLK cycles.
2.
Write the start hold-off counter(s) (0x83) to a value from 1
to 2
16
3.
Write the start bit and the applicable channel sync bit(s)
high at External Address 5. This triggers the start hold-off
counters to begin their count. The counters ar
with the AD6652 CLK signal. When it reaches a count of
one, the sleep bits of the selected channels are set low to
turn on the channel with the new or existing operating
parameters.
Note: Each channel has a redundant soft-sync control register
Address 0x81. This register mimics the programming as set in
the External Memory Address 5:5–4. The user can control the
soft-sync function of a DDC channel by writing to the 0x81
register, if it is adva
pin goes high (which
data) to
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相關代理商/技術參數(shù) |
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| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
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