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參數(shù)資料
| 型號： | AD6652BBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, BGA-256 |
| 文件頁數(shù)： | 48/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BBC |
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AD6652
Start with Pin Sync
The AD6652 provides four SYNC pins. A, B, C, and D, which are
used for very accurate channel synchronization. Each DDC
channel can be programmed to respond to any or all four syn
pins. Synchronization of start with one of the external sync pins
is accom
Rev. 0 | Page 48 of 76
c
plished with the following method. Refer to Figure 53
to assist in following this process.
1.
Place the channels to be programmed in sleep mode. The
AD6652 RESET
pin places all four DDC processing
channels in sleep mode when toggled low momentarily.
2.
Write the start hold-off counter(s) (0x83) to a value from 1
to 2
16
1. If the chip or channels have not been completely
programmed, write all other registers now.
3.
Set the Start_En bit high (External Address 4:4) and choose
which Pin Sync_En bits (External Address 4:3–0) are to be
used. Write the bit high to enable it.
4.
Set the sync input select bits
for each active channel
. This is
done at Address 0x88:8–7. Table 20 is the truth table for
these bits.
Table 20. Truth Table
0x88:8
0x88:7
0
0
0
1
1
0
1
1
Sync Pin Selected
A
B
C
D
After programming is complete and when the external si
attached to the selected sync p
hold-off counter of the chosen channel(s). The hold-off counte
begins counting using the AD6652 CLK signal. When it reaches
a count of 1, the sleep bit of the selected channel(s) is set low to
awaken the channel(s). Each
Pin Sync logic high
initiates a new
trigger event for the hold
External Addres
first sync signal is recognized and any others are disregard
until
First Sync Only
is reset.
gnal
in goes high, this triggers the start
r
-off counter unless
First Sync Only
,
s 4:6 is set to logic high. When high, only the
ed
at
pin
NCO
Sync
The AD6652 includes the ability to synchronize a change in
NCO frequency o
microport. The NC
onjunction with the hop bit and the sync bit (External
ddress 4) allows this synchronization. Basically, the NCO
equency hold-off counter delays the new frequency from
being loaded into the NCO by its value (number of AD6652
CLKs). Use the following method to synchronize a hop in
frequency of multiple channels via microprocessor control:
g the
er (0x84) in
1.
Write the NCO frequency hold-off counter (0x84) to the
appropriate value (greater than 0 and less then 2
16
).
2.
Write the NCO Frequency Register(s), 0x85 and 0x86, to
the new desired frequency.
3.
Write the hop bit and the applicable channel sync bit(s)
high at External Address 5.
This triggers the frequency hold-off counter(s) to begin their
count. The counters are clocked with the AD6652 CLK signal.
When it reaches a c
ount of 1, the new frequen
transferred from the shadow register to
the NCO. Unlike the start function, the
be placed in sleep mode to achieve a frequency hop.
cy data is
the working register of
channels do not need to
at
s the programming as set in
:5–4. The user can control the
Note: Each channel has a redundant pin-sync control register
Address 0x82. This register mimics the programming as set in
External Memory Address 4:6–4. The user can control the
sync function of a DDC channel by writing to Registers 0x82
and 0x88:8–7, if it is advantageous to do so in the application.
The time from when the pin sync goes high to when the DDC
channel resumes processing is equal to the time period set up by
the start hold-off counter value at 0x83 plus 3 CLK cycles.
HOP
Hop is a change from one NCO frequency to a new
frequency. This can apply to a single channel or multiple
channels and can be synchronized via microprocessor control
(soft sync) or an external sync signal (pin sync), as described in
the following sections. Awakening the channel from sleep mode
generates an internal start command that performs both hop
and start functions as if a soft-sync or pin-sync had been
received.
Hop with Soft
f multiple channels or chips usin
O frequency hold-off count
c
A
fr
Note: Each channel has a redundant soft-sync control register
Address 0x81. This register mimic
the External Memory Address 5
soft-sync function of a DDC channel by writing to the 0x81
register, if it is advantageous to do so in the application.
The time from when the DTACK pin goes high (which
acknowledges the receipt of the soft sync command data) to
when the DDC channel begins processing data is equal to th
time period set up by the frequency or hop
value at 0x84 plus 7 CLK cycles.
e
hold-off counter
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