參數(shù)資料
型號(hào)： AD6652BBC
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： 12-Bit, 65 MSPS IF to Baseband Diversity Receiver
中文描述： SPECIALTY TELECOM CIRCUIT, PBGA256
封裝： 17 X 17 MM, BGA-256
文件頁(yè)數(shù)： 55/76頁(yè)
文件大小： 1839K
代理商： AD6652BBC
AD6652
EXTERNAL MEMORY MAP
The external memory map is the
only
way to gain access to the
four channel address register pages and the output port control
register page. This set of eight registers is shown in Table 22.
These registers are collectively referred to as the external
memory map registers, because they control all accesses to the
channel address space as well as output control registers.
Rev. 0 | Page 55 of 76
The use of each of these individual registers is described in
detail in the following sections. It should be noted that the serial
control interface has the same memory map as the microport
interface and can carry out exactly the same functions, although
at a slower rate.
Table 22. External Memory Map
Address
Name
7
Access Control Register (ACR)
6
Channel Address Registers (CAR)
5
SOFT_SYNC Control Register (Write Only)
4
PIN_SYNC Control Register (Write Only)
3
SLEEP (Write Only)
2
Data Register 2 (DR2)
1
Data Register 1 (DR1)
0
Data Register 0 (DR0)
Comment
7:
6:
5–2:
1–0:
7–0:
7:
6:
5:
4:
3:
2:
1:
0:
7:
6:
5:
4:
3:
2:
1:
0:
7–6:
5:
4:
3:
2:
1:
0:
7–4:
3–0:
15–8:
7–0:
Auto increment
Broadcast
Instruction[3:0]
A[9:8]
A[7:0]
PN_EN
Test_MUX_Select
Hop
Start
SYNC CH3
SYNC CH2
SYNC CH1
SYNC CH0
Reserved write to logic low
First SYNC only
Hop_En
Start_En
PIN SYNC_EN D
PIN SYNC_EN C
PIN SYNC_EN B
PIN SYNC_EN A
Reserved write to logic low
Access output port control registers
Reserved low
SLEEP CH3
SLEEP CH2
SLEEP CH1
SLEEP CH 0
Reserved
D[19:16]
D[15:8]
D[7:0]
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