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參數(shù)資料
| 型號： | AD6652BBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, BGA-256 |
| 文件頁數(shù)： | 54/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BBC |
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AD6652
The length of the wait before data transm
programmable value in
0x1D Bits 6–3). This value allows the AD6652 PCLK
TigerSHARC PCLK to be run at different rates and
phase.
Rev. 0 | Page 54 of 76
ission is a 4-bit
the link port control registers (0x1B and
and the
out of
×
≥
TSHARC
LCLK
AD
LCLK
f
f
ciel
WAIT
_
6652
_
6
WAIT ensures that the amount of time the AD6652 needs to
wait to begin data transmission is at least equal to the minimum
amount of time the TigerSHARC is expecting it to wait. If the
PCLK of the AD6652 is
out of phase with the PCLK of the
TigerSHARC and the argument to the ceil() function is an
integer, then WAIT must be strictly greater than the value given
in the above formula.
If the LCLKs are in phase, then the maximum output data rate
is
TSHARC
LCLK
AD
LCLK
f
f
_
6652
_
6
15
×
≤
Otherwise, it is
TSHARC
LCLK
AD
LCLK
f
f
_
6652
_
6
14
×
≤
TIGERSHARC CONFIGURATION
Because the AD6652 is always the transmitter in this link and
the TigerSHARC is always the receiver, the following values can
be programmed into the LCTL register for the link port used t
receive AD6652 output data.
Table 21. TigerSHARC LCTLx Register Configuration
Register
Value
VERE
0
SPD
User
1
LTEN
0
PSIZE
1
TTOE
0
CERE
0
LREN
1
RTOE
1
o
1
The term
User
means that the actual register value depends on the user’s
application.
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| AD6652BC | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6652BBCZ | 功能描述:IC IF TO BASEBAND RCVR 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標準包裝:100 系列:* |
| AD6652BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
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| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
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