- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375235 > AD6652BBC (ANALOG DEVICES INC) 12-Bit, 65 MSPS IF to Baseband Diversity Receiver PDF資料下載
參數(shù)資料
| 型號： | AD6652BBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| 封裝： | 17 X 17 MM, BGA-256 |
| 文件頁數(shù)： | 31/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BBC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁
AD6652
CONTROL REGISTER AND
The following sections make frequent references to program-
mable registers and the memory mapping structure of the
AD6652. A good overview of the control registers and memory
mapping structure is found beginning in the External Mem
Map section. The following conventions are used in this
addressing scheme:
Rev. 0 | Page 31 of 76
MEMORY MAP ADDRE
N
ory
l register addresses that begin with 0x indicate that
that follows is in hexadecimal notation.
the address
dress
modate register data that is 20 bits wide;
can accom
however, many of the available 20 bits per address are
unused.
number(s), in decimal format, of the function that is being
described.
Eight, 3-bit external memory map addresses are shown in
decimal format in Table 22. Each of these addresses can
accommodate 8 bits of register data.
Decimal Addressing Example:
7:4 indicates that this is an
external memory address (no 0x prefix) and that the binary
address is 111, because only 3 external address bits are assigned.
Also, only Bit 4 of the 8-bit data field is described or referred to.
Hex Addressing Example:
0x0A:7–0 indicates that the binary
address is 00001010 and that Bits 7 through 0 are involved with
the function being described. Because this address begins with
0x, the user knows that it is not an external memory address,
and can be either an individual channel address register or an
output port control register, depending upon how it was routed
using the external memory address registers.
The largest 8-bit address that is used in the hexadecimal address
scheme is A9 or 169 decimal. This might not seem to be enough
memory addressing capacity, but, because addresses are re-used
with the external memory mapping scheme, there is no shortage
of address capability.
DDC INPUT MATRIX
The digital downconverter stages feature dual high speed
crossbar-switched input ports that allow the most flexibility in
routing the two ADC data streams to the four receive process-
ing channels. Crossbar switching means that any of the four
processing channels can receive data from either Port A or
Port B for a total of 16 possible combinations, as shown in
Table 12. Input port routing is selected in
each
NCO’s control
register at 0x88:6.
SS NOTATIO
Table 12. Crossbar-Switched Routing of the Two 12-Bit ADC
Data Streams (A and B) Using the DDC Input Matrix
Channel 3
Channel 2
A
A
A
A
A
A
A
A
A
B
A
B
A
B
A
B
B
A
B
A
B
A
B
A
B
B
B
B
B
B
B
B
Contro
cimal addresses are 8 bits wide, and each ad
All hexade
A colon following an address indicates the specific bit
Channel 1
A
A
B
B
A
A
B
B
A
A
B
B
A
A
B
B
Channel 0
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
DDC DATA LATENCY
The overall signal path latency from DDC input to output can
be expressed in high speed clock cycles. Use the following
equation to calculate the latency:
T
latency
= M
rCIC2
(M
CICS
+ 7) + N
taps
+ 26
where:
M
rCIC2
and
M
CIC5
are decimation values for the rCIC2 and CIC5
filters, respectively.
N
taps
is the number RCF taps chosen.
GAIN SWITCHING
The AD6652 includes circuitry that is useful in applications in
which large dynamic range input signals exist. This circuitry
allows digital thresholds to be set such that an upper and a
lower threshold can be programmed.
One use of this circuitry is to detect when an ADC is about to
reach full scale with a particular input condition. The results
provide a flag can quickly insert an attenuator to prevent ADC
overdrive. If 18 dB (or any arbitrary value) of attenuation (or
gain) is switched in, then the signal dynamic range of the
system is increased by 18 dB. The process begins when the input
signal reaches the upper programmed threshold. In a typical
application, this might be set 1 dB (user definable) below full
scale. When this input condition is met, the appropriate LI (LIA,
LIA, LIB or LIB) signal associated with either the A or B input
port is made active. This can be used to switch the gain or
attenuation of the external circuit. The LI line stays active until
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6652BC | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652PCB | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6816 | Interface For ATM User-Network Interface IC to Category #5 Unshielded Twisted Pair (UTP) system or a fiber optic system.(ATM用戶網(wǎng)絡(luò)接口與#5類非屏蔽雙絞線系統(tǒng)或其他光纖系統(tǒng)的接口芯片) |
| AD693(中文) | Loop-Powered 4-20 mA Sensor Transmitter(環(huán)路供電,4-20mA傳感器變送器) |
| AD7010ARS | MIL-spec connector accessory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6652BBCZ | 功能描述:IC IF TO BASEBAND RCVR 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:- 標(biāo)準(zhǔn)包裝:100 系列:* |
| AD6652BC | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
| AD6652BC/PCBZ | 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHA 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHANNEL RSP - Bulk |
| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。