VREFOUT Disable
參數(shù)資料
型號： AD1981BJST-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 24/32頁
文件大?。?/td> 0K
描述： IC CODEC STEREO MICPREAMP 48LQFP
標準包裝： 1
系列： SoundMAX®
類型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 16，20 b
ADC / DAC 數(shù)量： 4 / 2
三角積分調(diào)變： 無
動態(tài)范圍，標準 ADC / DAC (db)： 85 / 90
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 3 V ~ 3.47 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設(shè)備封裝： 48-LQFP（7x7）
包裝： 標準包裝
其它名稱： AD1981BJSTREELDKR
AD1981B
Rev. C | Page 30 of 32
Bit
Mnemonic
Function
VREFD
VREFOUT Disable
This bit disables VREFOUT, placing it into high Z out mode. This bit overrides the VREFH bit selection.
0 = VREFOUT pin is driven by the internal reference (reset default).
1 = VREFOUT pin is placed into high Z out mode.
VREFH
VREFOUT High
This bit changes VREFOUT from 2.25 V to 3.70 V for MIC bias applications.
0 = VREFOUT pin is set to 2.25 V output (reset default).
1 = VREFOUT pin is set to 3.70 V output.
MADST
Mixer ADC Status Bit
This bit indicates status of the mixer digitizing ADC (left and right channels).
0 = Mixer ADC not ready.
1 = Mixer ADC ready.
2CMIC
2-Channel MIC Select
This bit enables simultaneous recording from MIC1 and MIC2 inputs for applications that use a
stereo microphone array. This register works in conjunction with the MS bit in Register 0x20.
0 = MIC1 or MIC2 (determined by the MS bit) is routed to the record selector’s left and right MIC
channels, as well as to the mixer (reset default).
1 = MIC1 is routed to the record selector’s left MIC channel and MIC2 is routed to the record
selector’s right MIC channel. In this mode, the MS bit should be set low, and MIC1 can still be
enabled into the mixer.
MADPD
Mixer ADC Power-Down
This bit controls power-down for mixer digitizing ADC.
0 = Mixer ADC is powered on (default).
1 = Mixer ADC is powered down.
FMXE
Front DAC into Mixer
Enable
This bit controls the front (main) DAC to mixer mute switches.
0 = Front DAC outputs are allowed to sum into the mixer (reset default).
1 = Front DAC outputs are muted into the mixer (blocked).
DAM
Digital Audio Mode
PCM DAC outputs bypass the analog mixer and are sent directly to the codec output.
LODIS
LINE_OUT Disable
This bit disables the LINE_OUT pins (L/R), placing them into high Z mode so that the assigned
output audio jack can be shared for the input function (or other function).
0 = LINE_OUT pins have normal audio drive capability (reset default).
1 = LINE_OUT pins are placed into high Z mode.
MSPLT
Mute Split
This bit allows separate mute control bits for the master, headphone, LINE_IN, CD, AUX, and PCM
volume control registers as well as for the record gain register.
0 = Both left- and right-channel mutes are controlled by Bit 15 in the respective registers (reset
default).
1 = Bit 15 affects only the left-channel mute, and Bit 7 affects only the right-channel mute.
DACZ
DAC Zero-Fill
This bit determines DAC data fill under starved conditions.
0 = DAC data is repeated when DACs are starved for data (reset default).
1 = DAC is zero-filled when DACs are starved for data.
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1981BJSTZ 制造商:Analog Devices 功能描述:IC AUDIO CODEC
AD1981BJSTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec
AD1981BJSTZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX Codec
AD1981BJSTZ-REEL 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:AC'97 SOUNDMAX CODEC W/STEREO MIC PREAMP - Tape and Reel 制造商:Analog Devices 功能描述:IC AUDIO CODEC
AD1981BJSTZ-REEL2 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX Codec
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