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參數(shù)資料
| 型號： | AD1981BJST-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/32頁 |
| 文件大小： | 0K |
| 描述： | IC CODEC STEREO MICPREAMP 48LQFP |
| 標準包裝： | 1 |
| 系列： | SoundMAX® |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 16，20 b |
| ADC / DAC 數(shù)量： | 4 / 2 |
| 三角積分調(diào)變： | 無 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 85 / 90 |
| 電壓 - 電源，模擬： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.47 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD1981BJSTREELDKR |
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AD1981B
Rev. C | Page 21 of 32
POWER-DOWN CONTROL/STATUS REGISTER
Index 0x26
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x26
Power-Down Ctrl/Stat
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
X
REF
ANL
DAC
ADC
0x000X
The ready bits are read-only; writing to REF, ANL, DAC, ADC has no effect. These bits indicate the status for the AD1981B subsections. If the bit is a 1, that subsection is
ready. Ready is defined as the subsection able to perform in its nominal state.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 28.
Bit
Mnemonic
Function
ADC
ADC Sections Ready to Transmit Data.
DAC
DAC Sections Ready to Accept Data.
ANL
Analog Amplifiers, Attenuators, and Mixers Ready.
REF
Voltage References, VREF and VREFOUT, Up to Nominal Level.
PR [6:0]
Codec Power-
Down Modes
The first three bits are to be used individually rather than in combination with each other. PR3 can be
used in combination with PR2 or by itself. The mixer and reference cannot be powered down via PR3
unless the ADCs and DACs are also powered down.
Nothing else can be powered up until the reference is powered up. PR5 has no effect unless all ADCs,
DACs, and the ac-link are powered down. The reference and the mixer can be either powered up or
powered down, but all power-up sequences must be allowed to run to completion before PR5 and PR4
are both set.
In multiple codec systems, the master codec’s PR5 and PR4 bits control the slave codec. PR5 is also
effective in the slave codec, if the master’s PR5 bit is clear, but the PR4 bit has no effect except to enable or
disable PR5.
EAPD
External Audio
Power-Down
Control
Controls the state of the EAPD pin.
EAPD = 0 sets the EAPD pin low, enabling an external power amplifier (reset default).
EAPD = 1 sets the EAPD pin high, shutting the external power amplifier off.
Table 29.
Power-Down State
Set Bits
PR [6:0]
ADCs and Input MUX Power-Down
PR0
[000 0001]
DACs Power-Down
PR1
[000 0010]
Analog Mixer Power-Down (VREF and VREFOUT On)
PR1, PR2
[000 0101]
Analog Mixer Power-Down (VREF and VREFOUT Off)
PR0, PR1, PR3
[000 1011]
AC-Link Interface Power-Down
PR4
[001 0000]
Internal Clocks Disabled
PR0, PR1, PR4, PR5
[011 0011]
ADC and DAC Power-Down
PR0, PR1
[000 0011]
VREF Standby Mode
PR0, PR1, PR2, PR4, PR5
[011 0111]
Total Power-Down
PR0, PR1, PR2, PR3, PR4, PR5, PR6
[111 1111]
Headphone Amp Power-In Standby
PR6
[100 0000]
OBSOLETE
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