參數(shù)資料
型號(hào)： AD1981BJST-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/32頁(yè)
文件大?。?/td> 0K
描述： IC CODEC STEREO MICPREAMP 48LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SoundMAX®
類型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 16，20 b
ADC / DAC 數(shù)量： 4 / 2
三角積分調(diào)變： 無(wú)
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 85 / 90
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 3 V ~ 3.47 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD1981BJSTREELDKR
AD1981B
Rev. C | Page 29 of 32
SERIAL CONFIGURATION REGISTER
Index 0x74
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x74
Serial
Config
SLOT16
REGM2
REGM1
REGM0
X
CHEN
X
INTS
X
SPAL
SPDZ
SPLNK
0x7001
This register is not reset when the reset register (Register 0x00) is written.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 42.
Bit
Mnemonic
Function
SPLNK
SPDIF Link
This bit enables the SPDIF to link with the DAC for data requests.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
SPDZ
SPDIF DACZ
0 = Repeat last sample out of the SPDIF stream if FIFO underruns (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO underruns.
SPAL
SPDIF ADC Loop-
Around
0 = SPDIF transmitter is connected to the ac-link stream (reset default).
1 = SPDIF transmitter is connected to the digital ADC stream, not the ac-link.
INTS
Interrupt Mode Select
This bit selects the JS interrupt implementation path.
0 = Bit 0 Slot 12 (modem interrupt).
1 = Slot 6 valid bit (MIC ADC interrupt).
CHEN
Chain Enable
This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
REGM0
Master Codec Register
Mask
REGM1
Slave 1 Codec Register
Mask
REGM2
Slave 2 Codec Register
Mask
SLOT16
Enable 16-Bit Slot Mode
Slot 16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a preferred mode for
DSP serial port interfacing.
MISCELLANEOUS CONTROL BIT REGISTER
Index 0x76
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x76
Misc
Control
Bit
DACZ
X
MSPLT
LODIS
DAM
X
FMXE
X
MADPD
2CMIC
X
MADST
VREFH
VREFD
MBG1
MBG0
0x0000
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 43.
Bit
Mnemonic
Function
MBG [1:0]
MIC Boost Gain Change
Register
These two bits allow changing the MIC preamp gain from the nominal 20 dB gain.
This gain setting takes effect only while Bit D6 (M20) on the MIC volume register (0x0E) is set to 1;
otherwise, the MIC boost block has a gain of 0 dB.
00 = 20 dB gain (reset default).
01 = 10 dB gain.
10 = 30 dB gain.
11 = Reserved.
OBSOLETE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1981BJSTZ 制造商:Analog Devices 功能描述:IC AUDIO CODEC
AD1981BJSTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec
AD1981BJSTZ2 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX Codec
AD1981BJSTZ-REEL 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:AC'97 SOUNDMAX CODEC W/STEREO MIC PREAMP - Tape and Reel 制造商:Analog Devices 功能描述:IC AUDIO CODEC
AD1981BJSTZ-REEL2 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX Codec
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