參數(shù)資料
型號： AD1981BJST-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 19/32頁
文件大?。?/td> 0K
描述： IC CODEC STEREO MICPREAMP 48LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SoundMAX®
類型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 16，20 b
ADC / DAC 數(shù)量： 4 / 2
三角積分調(diào)變： 無
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 85 / 90
電壓 - 電源，模擬： 4.5 V ~ 5.5 V
電壓 - 電源，數(shù)字： 3 V ~ 3.47 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD1981BJSTREELDKR
AD1981B
Rev. C | Page 26 of 32
EQ DATA REGISTER
Index 0x62
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x62
EQ
Data
CFD15
CFD14
CFD13
CFD12
CFD11
CFD10
CFD9
CFD8
CFD7
CFD6
CFD5
CFD4
CFD3
CFD2
CFD1
CFD0
0x0000
This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved from, the address pointed to by the BCA
bits in the EQ Cntrl Register (0x60). Data is written to memory only if the EQM bit (Register 0x60, Bit 15) is asserted.
Table 37.
Bit
Mnemonic
Function
CFD [15:0]
Coefficient Data
The biquad coefficients are fixed-point format values with 16 bits of resolution. The CFD15 bit is
the MSB, and the CFD0 bit is the LSB.
MIXER ADC, INPUT GAIN REGISTER
Index 0x64
Reg
No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x64
Mixer ADC,
Volume
MXM
X
LMG3
LMG2
LMG1
LMG0
RM1
X
RMG3
RMG2
RMG1
RMG0
0x8000
1For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect. All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 39 for examples.
Table 38.
Bit
Mnemonic
Function
RMG [3:0]
Right Mixer Gain
Control
This register controls the gain into the mixer ADC from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
RM
Right-Channel Mute
Once enabled by the MSPLT bit in Register 0x76, this bit mutes the right channel separately from
the MXM bit. Otherwise, this bit always reads 0 and has no affect when set to 1.
LMG [3:0]
Left Mixer Gain Control
This register controls the gain into the mixer ADC, from 0 dB to a maximum gain of 22.5 dB. The
least significant bit represents 1.5 dB.
MXM
Mixer Gain Register
Mute
0 = Unmuted.
1 = Muted (reset default).
Table 39. Settings for Mixer ADC, Input Gain
Reg. 0x76
Control Bits Mixer ADC, Input Gain (0x64)
Left-Channel Mixer Gain D [11:8]
Right-Channel Mixer Gain D [3:0]
MSPLT1
D15
Write
Readback
Function
D71
Write
Readback
Function
0
1111
22.5 dB Gain
X
1111
22.5 dB Gain
0
0000
0 dB Gain
X
0000
0 dB Gain
0
1
XXXX
∞ dB Gain, Muted
X
XXXX
∞ dB Gain, Muted
1
0
1111
22.5 dB Gain
1
XXXX
∞ dB Gain, Right Only Muted
1
XXXX
∞ dB Gain, Left Only Muted
0
1111
22.5 dB Gain
1
XXXX
∞ dB Gain, Left Muted
1
XXXX
∞ dB Gain, Right Muted
1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate mute bits for the left and right channels.
If MSPLT is not set, the RM bit has no effect.
X is a wild card and has no effect on the value.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1981BJSTZ 制造商:Analog Devices 功能描述:IC AUDIO CODEC
AD1981BJSTZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec
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AD1981BJSTZ-REEL2 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX Codec
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