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參數(shù)資料
| 型號： | AD1981BJST-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC STEREO MICPREAMP 48LQFP |
| 標準包裝： | 1 |
| 系列： | SoundMAX® |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 16，20 b |
| ADC / DAC 數(shù)量： | 4 / 2 |
| 三角積分調變： | 無 |
| 動態(tài)范圍，標準 ADC / DAC (db)： | 85 / 90 |
| 電壓 - 電源，模擬： | 4.5 V ~ 5.5 V |
| 電壓 - 電源，數(shù)字： | 3 V ~ 3.47 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD1981BJSTREELDKR |
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AD1981B
Rev. C | Page 24 of 32
SPDIF CONTROL REGISTER
Index 0x3A
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x3A
SPDIF Control
V
X
SPSR1
SPSR0
L
CC6
CC5
CC4
CC3
CC2
CC1
CC0
PRE
COPY
AUD
PRO
0x2000
Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the V case). With the
exception of V, this register should be written to only when the SPDIF transmitter is disabled (SPDIF bit in Register 0x2A is 0). This ensures that control and status
information start up correctly at the beginning of SPDIF transmission.
Table 35.
Bit
Mnemonic
Function
PRO
Professional
1 = Professional use of channel status.
0 = Consumer.
AUD
Nonaudio
1 = Data is non-PCM format.
0 = Data is PCM format.
COPY
Copyright
1 = Copyright is asserted.
0 = Copyright is not asserted.
PRE
Pre-emphasis
1 = Filter pre-emphasis is 50 s/15 s.
0 = Pre-emphasis is none.
CC [6:0]
Category Code
Programmed according to IEC standards, or as appropriate.
L
Generation Level
Programmed according to IEC standards, or as appropriate.
SPSR [1:0]
SPDIF Transmit
Sample Rate
SPSR [1:0] = 00: Transmit sample rate is 44.1 kHz.
SPSR [1:0] = 01: Reserved.
SPSR [1:0] = 10: Transmit sample rate is 48 kHz (reset default).
SPSR [1:0] = 11: Not supported.
V
Validity
This bit affects the validity flag (Bit 28 transmitted in each SPDIF L/R subframe) and enables the SPDIF
transmitter to maintain connection during error or mute conditions.
V = 1: Each SPDIF subframe (L + R) has Bit 28 set to 1. This tags both samples as invalid.
V = 0: Each SPDIF subframe (L + R) has Bit 28 set to 0 for valid data and 1 for invalid data (error
condition).
When V = 0, asserting the VFORCE bit (D15) in Register 0x2A (Ext’d Audio Stat/Ctrl) forces the validity
flag low, marking both samples as valid.
EQ CONTROL REGISTER
Index 0x60
Reg No.
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
0x60
EQ Ctrl
EQM
MAD LBEN
X
SYM
CHS
BCA5
BCA4
BCA3
BCA2
BCA1
BCA0
0x8080
Register 0x60 is a read/write register that controls the equalizer functionality and data setup. This register contains the biquad and coefficient address pointer, which
is used in conjunction with the EQ data register (0x78) to set up the equalizer coefficients. The reset default disables the equalizer function until the coefficients can be
properly set up by the software and sets the symmetry bit to allow equal coefficients for left and right channels.
All registers are not shown, and bits containing an X are assumed to be reserved.
Table 36.
Bit
Mnemonic
Function
BCA [5:0]
Biquad and Coefficient
Address Pointer
biquad 0 coef a0 BCA[5:0] = 011011
biquad 0 coef a1 BCA[5:0] = 011010
biquad 0 coef a2 BCA[5:0] = 011001
biquad 0 coef b1 BCA[5:0] = 011101
biquad 0 coef b2 BCA[5:0] = 011100
biquad 1 coef a0 BCA[5:0] = 100000
biquad 1 coef a1 BCA[5:0] = 011111
OBSOLETE
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相關代理商/技術參數(shù) |
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|---|---|
| AD1981BJSTZ | 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD1981BJSTZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC 97 SoundMAX Codec |
| AD1981BJSTZ2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX Codec |
| AD1981BJSTZ-REEL | 制造商:Analog Devices 功能描述:Audio Codec 4ADC / 2DAC 20-Bit 48-Pin LQFP T/R 制造商:Rochester Electronics LLC 功能描述:AC'97 SOUNDMAX CODEC W/STEREO MIC PREAMP - Tape and Reel 制造商:Analog Devices 功能描述:IC AUDIO CODEC |
| AD1981BJSTZ-REEL2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:AC ’97 SoundMAX Codec |
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