參數(shù)資料
型號(hào)： AD1843JS
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CAP 3300PF 100V CERAMIC DISC Y5P
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 9/64頁
文件大?。?/td> 848K
代理商： AD1843JS
AD1843
REV. 0
–9–
Analog Signals
Pin Name
PQFP
TQFP
I/O
Description
LINLP
LINLN
LINRP
LINRN
MICL
28
29
26
27
18
35
36
33
34
21
I
I
I
I
I
Line Input Left Channel Positive Differential Signal.
Line Input Left Channel Negative Differential Signal.
Line Input Right Channel Positive Differential Signal.
Line Input Right Channel Negative Differential Signal.
Microphone Input Left Channel. Microphone input for the left channel. This
signal can be either line level or –20 dB from line level.
Microphone Input Right Channel. Microphone input for the right channel.
This signal can be either line level or –20 dB from line level.
Auxiliary #1 Left Channel Line Input.
Auxiliary #1 Right Channel Line Input.
Auxiliary #2 Left Channel Line Input.
Auxiliary #2 Right Channel Line Input.
Auxiliary #3 Left Channel Line Input.
Auxiliary #3 Right Channel Line Input.
Monaural (Mono) Line Input.
Monaural (Mono) Line Output.
Line Output #1 Left Channel.
Line Output #1 Right Channel.
Headphone Output Left Channel.
Headphone Common Return.
Headphone Output Right Channel.
Line Output #2 Left Channel Positive Differential Signal.
Line Output #2 Left Channel Negative Differential Signal.
Line Output #2 Right Channel Positive Differential Signal.
Line Output #2 Right Channel Negative Differential Signal.
Mixer Line Input Left Channel.
Mixer Line Input Right Channel.
MICR
17
22
I
AUX1L
AUX1R
AUX2L
AUX2R
AUX3L
AUX3R
MIN
MOUT
LOUT1L
LOUT1R
HPOUTL
HPOUTC
HPOUTR
LOUT2LP
LOUT2LN
LOUT2RP
LOUT2RN
SUML
SUMR
16
15
14
13
12
11
19
35
36
34
47
46
45
32
33
30
31
43
42
20
19
18
17
16
15
23
44
45
43
58
57
56
40
41
38
39
54
53
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
I
I
Clocks
Pin Name
PQFP
TQFP
I/O
Description
CLKOUT
76
95
O
Clock Output. This signal is a buffered version of XTALO (with a duty cycle
restored to at least 60%/40%), the crystal clock output. This pin is enabled by
default but can be three-stated by programming a bit in Control Register
Address 28. The CLKOUT frequency is 24.576 MHz.
Sync Inputs. These SYNC signals are used as the clock source inputs to three
receptive PLLs in the AD1843. These pins accept a clock at, or at a multiple of,
the desired sample rate for A-to-D and D-to-A conversions. These inputs are
ignored if a sample rate is programmed directly, but should never be left floating.
Conversion Clock Outputs. These output clocks have an average period equal to (or 128
times) the internal sample rates of the AD1843. These clock outputs are three-stated
by default but can be enabled by programming bits in Control Register Address 28.
Bit Clock Outputs. These output clocks can be individually programmed to
multiples of the sample rates. Support for V.34 or V.32 bit rates is available.
These clock outputs are three-stated by default but can be enabled by
programming bits in Control Register Address 28.
SYNC[3:1]
57, 56, 55
71, 70, 69
I
CONV[3:1]
75, 71, 67
94, 89, 84
O
BIT[3:1]
74, 70, 66
92, 87, 82
O
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1843JST 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundComm Codec
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AD1845JP-REEL 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC T/R
AD1845JPZ 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC
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