參數(shù)資料
型號(hào)： AD1843JS
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CAP 3300PF 100V CERAMIC DISC Y5P
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 34/64頁(yè)
文件大?。?/td> 848K
代理商： AD1843JS
REV. 0
–34–
AD1843
LDA1G5:0
Left DAC1 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the
implementation of the attenuation is mixed analog and digital.
0 00000 =
+12.0 dB:
+12.0 dB Analog,
0 01000
=
0.0 dB:
+0.0 dB Analog,
0 11111 =
–34.5 dB:
–34.5 dB Analog,
1 00000 =
–36.0 dB:
–34.5 dB Analog,
1 11111 =
–82.5 dB:
–34.5 dB Analog,
Right DAC1 Analog Mute
0 = Right DAC1 Enabled
1
= Right DAC1 Muted
Right DAC1 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the
implementation of the attenuation is mixed analog and digital.
0 00000 =
+12.0 dB:
+12.0 dB Analog,
0 01000
=
0.0 dB:
+0.0 dB Analog,
0 11111 =
–34.5 dB:
–34.5 dB Analog,
1 00000 =
–36.0 dB:
–34.5 dB Analog,
1 11111 =
–82.5 dB:
–34.5 dB Analog,
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the
RESET
pin is asserted LO; when the
PWRDWN
pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); when the ANAEN bit in Control Register Address 27 is reset to “0”
(analog channels powered down); or when the DA1EN bit in Control Register Address 27 is reset to “0” (DAC1
disabled).
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
RDA1GM
RDA1G5:0
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
res
Address 10
Output Control—DAC2 Analog Gain/Attenuation
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
LDA2GM
res
LDA2G5
LDA2G4
LDA2G3
LDA2G2
LDA2G1
LDA2G0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
RDA2GM
res
RDA2G5
RDA2G4
RDA2G3
RDA2G2
RDA2G1
RDA2G0
LDA2GM
Left DAC2 Analog Mute
0 = Left DAC2 Enabled
1
= Left DAC2 Muted
Left DAC2 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the imple-
mentation of the attenuation is mixed analog and digital.
0 00000 =
+12.0 dB:
+12.0 dB Analog,
0 01000
=
0.0 dB:
+0.0 dB Analog,
0 11111 =
–34.5 dB:
–34.5 dB Analog,
1 00000 =
–36.0 dB:
–34.5 dB Analog,
1 11111 =
–82.5 dB:
–34.5 dB Analog,
Right DAC2 Analog Mute
0 = Right DAC2 Enabled
1
= Right DAC2 Muted
Right DAC2 Analog/Digital Gain/Attenuation Select. Least significant bit represents –1.5 dB. Note that the imple-
mentation of the attenuation is mixed analog and digital.
0 00000 =
+12.0 dB:
+12.0 dB Analog,
0 01000
=
0.0 dB:
+0.0 dB Analog,
0 11111 =
–34.5 dB:
–34.5 dB Analog,
1 00000 =
–36.0 dB:
–34.5 dB Analog,
1 11111 =
–82.5 dB:
–34.5 dB Analog,
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the
RESET
pin is asserted LO; when the
PWRDWN
pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); when the ANAEN bit in Control Register Address 27 is reset to “0”
(analog channels powered down); or when the DA2EN bit in Control Register Address 27 is reset to “0” (DAC2
disabled).
LDA2G5:0
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
RDA2GM
RDA2G5:0
+0.0 dB Digital
+0.0 dB Digital
+0.0 dB Digital
–1.5 dB Digital
–48.0 dB Digital
res
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