參數(shù)資料
型號(hào)： AD1843JS
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： CAP 3300PF 100V CERAMIC DISC Y5P
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁(yè)數(shù)： 50/64頁(yè)
文件大小： 848K
代理商： AD1843JS
REV. 0
–50–
AD1843
C2EN
Clock Generator 2 Enable/Power Down.
0
= Clock Generator 2 Powered Down
1 = Clock Generator 2 Enabled
Clock Generator 1 Enable/Power Down.
0
= Clock Generator 1 Powered Down
1 = Clock Generator 1 Enabled
CLKOUT Pin Enable.
0 = Clock Output is Three-stated (Powered Down)
1
= Clock Output is Enabled
External Control. The state of these independent bits is reflected on the respective XCTL1 and XCTL0 output pins.
0
= TTL Logic Level LO on XCTL1/XCTL0 pin
1 = TTL Logic Level HI on XCTL1/XCTL0 pin
CONV3 Pin Enable.
0
= CONV3 is Three-stated (Powered Down)
1 = CONV3 is Enabled
BIT3 Pin Enable.
0
= BIT3 is Three-stated (Powered Down)
1 = BIT3 is Enabled
CONV2 Pin Enable.
0
= CONV2 is Three-stated (Powered Down)
1 = CONV2 is Enabled
BIT2 Pin Enable.
0
= BIT2 is Three-stated (Powered Down)
1 = BIT2 is Enabled
CONV1 Pin Enable.
0
= CONV1 is Three-stated (Powered Down)
1 = CONV1 is Enabled
BIT1 Pin Enable.
0
= BIT1 is Three-stated (Powered Down)
1 = BIT1 is Enabled
Line Input Right Channel Single-Ended or Differential Configuration.
0
= Right Channel Line Input is Single-Ended
1 = Right Channel Line Input is Differential
Line Input Left Channel Single-Ended or Differential Configuration.
0
= Left Channel Line Input is Single-Ended
1 = Left Channel Line Input is Differential
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1100 0100 0000 0000 (C400 hex). Cleared to default and cannot be written to when:
the
RESET
pin is asserted LO; or when the
PWRDWN
pin is asserted LO.
C1EN
ENCLKO
XCTL1:0
ENCV3
ENBT3
ENCV2
ENBT2
ENCV1
ENBT1
LINRSD
LINLSD
res
Address 29
Reserved for Future Expansion
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
res
res
res
res
res
res
res
res
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
res
res
res
res
res
res
res
res
res
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:
the
RESET
pin is asserted LO; or when the
PWRDWN
pin is asserted LO.
相關(guān)PDF資料
PDF描述
AD1843JST Serial-Port 16-Bit SoundComm Codec
AD1846JP Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec
AD1849KP Serial-Port 16-Bit SoundPort Stereo Codec
AD1851 16-Bit, 16×Fs PCM Audio DACs(16位,單片PCM音頻D/A轉(zhuǎn)換器)
AD1892JR Integrated Digital Receiver/Rate Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD1843JST 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial-Port 16-Bit SoundComm Codec
AD1845 制造商:AD 制造商全稱:Analog Devices 功能描述:Parallel-Port 16-Bit SoundPort Stereo Codec
AD1845JP 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC 制造商:Rochester Electronics LLC 功能描述:16 BIT AUDIO CODEC - Bulk 制造商:Analog Devices 功能描述:IC CODEC 16-BIT AUDIO
AD1845JP-REEL 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC T/R
AD1845JPZ 制造商:Analog Devices 功能描述:Audio Codec 2ADC / 2DAC 16-Bit 68-Pin PLCC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*