參數(shù)資料
型號： AD1843JS
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： CAP 3300PF 100V CERAMIC DISC Y5P
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： PLASTIC, QFP-80
文件頁數(shù)： 32/64頁
文件大?。?/td> 848K
代理商： AD1843JS
REV. 0
–32–
AD1843
RX3MM
Right Auxiliary 3 Mix Mute
0 = Mix Enabled
1
= Mix Muted
Right Auxiliary 3 Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to
2.0 V p-p DAC1 output level.
00000 = +12.0 dB Gain
01000
= 0.0 dB
11111 = –34.5 dB Attenuation
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the
RESET
pin is asserted LO; when the
PWRDWN
pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to analog mix disabled), or
the ANAEN bit (analog channels powered down) in Control Register Address 27 is reset to “0.”
RX3M4:0
res
Address 7
Mix Control—Mic to Mixer
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
LMCMM
res
res
LMCM4
LMCM3
LMCM2
LMCM1
LMCM0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
RMCMM
res
res
RMCM4
RMCM3
RMCM2
RMCM1
RMCM0
LMCMM
Left Microphone Mix Mute
0 = Mix Enabled
1
= Mix Muted
Left Microphone Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p
DAC1 output level.
00000 = +12.0 dB Gain
01000
= 0.0 dB
11111 = –34.5 dB Attenuation
Right Microphone Mix Mute
0 = Mix Enabled
1
= Mix Muted
Right Microphone Mix Gain/Attenuation Select. Least significant bit represents –1.5 dB. Referred to 2.0 V p-p
DAC1 output level.
00000 = +12.0 dB Gain
01000
= 0.0 dB
11111 = –34.5 dB Attenuation
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 1000 1000 1000 1000 (8888 hex). Cleared to default and cannot be written to when:
the
RESET
pin is asserted LO; when the
PWRDWN
pin is asserted LO; when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled); or when the AAMEN bit (analog input to analog mix disabled), or
the ANAEN bit (analog channels powered down) in Control Register Address 27 is reset to “0.”
LMCM4:0
RMCMM
RMCM4:0
res
Address 8
Mix/Miscellaneous Control—Mono In to Mixer and Miscellaneous Settings
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
MNMM
res
res
MNM4
MNM3
MNM2
MNM1
MNM0
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
ALLMM
MNOM
HPOM
HPOS
SUMM
res
DAC2T
DAC1T
MNMM
Mono Input Mix Mute
0 = Mix Enabled
1
= Mix Muted
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