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參數(shù)資料
| 型號： | ACS8946T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 39/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 8
www.semtech.com
ACS8946 JAM PLL
The ACS8946 is a low-jitter integrated PLL for dejittering
and clock rate translation, meeting the jitter requirements
for SONET up to and including OC-12 (622.08 MHz)
systems. It is compliant to the relevant ITU,
Telcordia/Bellcore and ETSI standards for at least OC-3
(155.52 MHz) and OC-12 (622.08 MHz) - equivalent to
the corresponding STM1 and 4 rates. It may also be used
as an initial clock clean-up device in, for example, in
OC-48 systems, where the CMU PLL in the
Serializer/Framer has a suitable bandwidth.
The ACS8946 can be configured for a range of
applications using a minimal number of external
components and is available in a small form factor QFN48
package at 7 mm x 7 mm x 0.9 mm outer dimensions.
An evaluation board and GUI software is available on
request for hands-on device assessment.
Figure 3 Example EVB GUI Software
Inputs
The ACS8946 has two LVPECL differential inputs
(CLK1N/P, pins 27 and 28, and CLK2N/P, pins 30 and
31). These are programmable to accept input frequencies
of 19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz,
155.52 MHz or 156.25 MHz. Frequencies near to these
spot frequencies can also be accepted (see Table 5) so
long as the chosen frequency supplied to each input
remains stable to within the ±400 ppm tracking range.
LVDS and CML inputs can be accepted given suitable
passive resistive and capacitive interface components.
Phase comparisons are performed directly at the selected
spot frequency rates in the internal Phase and Frequency
Detector (PFD), unless GbE (Gigabit Ethernet) rates are
selected for output rates, in which case the input
frequencies are divided as required prior to the PFD.
Either clock input may be manually or automatically
selected as the reference based on the detection of clock
activity at the inputs. The signals AUTO_SEL and
SEL_CLK2, shown in Table 4, are used to control the input
clock selection. In automatic mode the clock selection
between CLK1 and CLK2 is non-revertive, i.e. if the PLL is
locked onto CLK1 and CLK1 fails so that the PLL switches
over to CLK2, then when CLK1 becomes operational
again the PLL will not switch back to CLK1.
Configuration of expected input clock frequency, which
has to be the same for both clock inputs, is set by the
wiring of configuration pins described in Table 10.
Unused differential inputs from CLK[2:1]N/P and
SYNCN/P should be wired P to GND and N to VDD.
In addition to the main clock inputs CLK1, and CLK2, a
single differential SYNC input is provided.
The permitted input frequency range either side of the
selected spot frequency depends on the input clock rate.
Table 5 presents the list of configurable input spot
frequencies, and shows the maximum and minimum
range about each input spot frequency that can be
allowed as input to the device as a percentage of the
configured input spot frequency.
An External Feedback mode is available and may be used
for greater control of phase discrepancies for example
when using external buffers. In External Feedback mode
the external feedback signal is received at the CLK2 input,
hence CLK1 can be the only input in this mode.
Outputs
The ACS8946 has four, LVPECL or CML, differential
outputs: OUT[4:1]N/P, pins 11/12, 8/9, 5/6, and 2/3.
Outputs are produced in a CML or LVPECL output format
on up to four outputs concurrently. Interfacing to LVDS is
Description
Table 4 Input Selection Decoding
AUTO_SEL SEL_CLK2
Selected
Reference
Feedback Clock
0
CLK1
Internal Path
0
1
CLK2
Internal Path
1
0
CLK1
CLK2
1
AUTOMATIC
SELECTION
(Activity Monitor
determines)
Internal Path
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