- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1978 > ACS8946T (Semtech)IC JITTER ATT MULT PLL 48-QFN PDF資料下載
參數(shù)資料
| 型號： | ACS8946T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 37/40頁 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 6
www.semtech.com
ACS8946 JAM PLL
24
CFG_IN6
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 25 to
to set the value of the odd divider, which applies a division of 1/3/5/7/9/11/13 or 15 to
the otherwise selected spot frequency, on each of the four outputs OUTN/P[4:1]. It is also
used to enable or disable the lock detector (pin 17 LOCKB), and to set the output pad
mode (CML or PECL) for OUT3 and OUT4 as shown in Table 13.
25
CFG_IN7
I
LVTTL/
LVCMOSD
Configuration pin for setting up the device just after power-up or after a system reset (via
pin 40, RESETB). This configuration pin is analyzed during the configuration phase, just
after power-up, so that the device works out whether this pin is connected to ground,
power or one of the configuration outputs at pins 13 to 16. This pin is used with pin 24 to
to set the value of the odd divider, which applies a division of 1/3/5/7/9/11/13 or 15 to
the otherwise selected spot frequency on each of the four outputs OUTN/P[4:1]. It is also
used to enable or disable the lock detector (pin 17 LOCKB) and to set the output pad
mode (CML or PECL) for OUT3 and OUT4 as shown in Table 13.
27
CLK1N
I
LVPECL
Input reference clock that the PLL will phase and frequency lock to. Can accept
19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz, and
frequencies near to these so long as the chosen frequency remains stable to within the
tracking range of ±400 ppm. (See “Inputs” on page 8 and Table 10). Can accept LVPECL
or LVDS or CML inputs given suitable external interface components. Partnered with pin
28. This clock or CLK2 can be automatically or manually selected as the reference clock,
see Table 4.
28
CLK1P
I
LVPECL
Input reference clock that the PLL will phase and frequency lock to. Can accept
19.44 MHz, 38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz and
frequencies near to these so long as the chosen frequency remains stable to within the
tracking range of ±400 ppm. (See “Inputs” on page 8 and Table 10). Can accept LVPECL
or LVDS or CML inputs given suitable external interface components. Partnered with pin
27. This clock or CLK2 can be automatically or manually selected as the reference clock,
see Table 4.
30
CLK2N
I
LVPECL
Second Input reference clock that the PLL will phase and frequency lock to. Input
reference clock that the PLL will phase and frequency lock to. Can accept 19.44 MHz,
38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz, and frequencies
near to these so long as the chosen frequency remains stable to within the tracking
range of ±400 ppm. (See “Inputs” on page 8 and Table 10). Can accept LVPECL or LVDS
or CML inputs given suitable external interface components. Partnered with pin 31. This
clock or CLK1 can be automatically or manually selected as the reference clock, see
31
CLK2P
I
LVPECL
Second Input reference clock that the PLL will phase and frequency lock to. Input
reference clock that the PLL will phase and frequency lock to. Can accept 19.44 MHz,
38.88 MHz, 77.76 MHz, 125.00 MHz, 155.52 MHz or 156.25 MHz, and frequencies
near to these so long as the chosen frequency remains stable to within the tracking
range of ±400 ppm. (See “Inputs” on page 8 and Table 10). Can accept LVPECL or LVDS
or CML inputs given suitable external interface components. Partnered with pin 30. This
clock or CLK2 can be automatically or manually selected as the reference clock, see
32
SEL_CLK2
I
LVTTL/
LVCMOSD
Used in combination with pin 33, AUTO_SEL, either to select the CLK2 clock (high) or
CLK1 clock (low) in manual control mode, or to select automatic switching mode, as
described in Table 4.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ACS8947T | IC JITTER ATT MULT PLL 48-QFN |
| AD10200BZ | IC ADC DUAL 12BIT 68-CLCC |
| AD10242BZ | IC ADC DUAL 12BIT 68-CLCC |
| AD10465BZ | IC ADC DUAL 14BIT 68-CLCC |
| AD13280AZ | IC ADC 12BIT 68CLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACS8947T | 功能描述:IC JITTER ATT MULT PLL 48-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| ACS9010 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| ACS9510/50EVB | 制造商:Semtech Corporation 功能描述: |
| ACS9510EVB | 功能描述:EVALUATION BOARD FOR ACS9510 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:ToPSync™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| ACS9510T | 制造商:Semtech Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。