Note...A= A" />
參數(shù)資料
型號(hào)： ACS8946T
廠商： Semtech
文件頁(yè)數(shù)： 38/40頁(yè)
文件大小： 0K
描述： IC JITTER ATT MULT PLL 48-QFN
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH
輸入： LVPECL
輸出： CML，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 625MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-QFN（7x7）
包裝： 托盤(pán)
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 7
www.semtech.com
ACS8946 JAM PLL
Note...A= Analog, I = Input, O = Output, P = Power, LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up resistor, LVTTL/LVCMOSD =
LVTTL/LVCMOS input with pull-down resistor.
33
AUTO_SEL
I
LVTTL/
LVCMOSD
Used in combination with pin 32, SEL_CLK2, to select automatic switching mode, as
described in Table 4.
35
VCP
A
Analog
Connection for external loop filter components. This is the differential control voltage
input to the internal VCO and the internal differential charge pump output up to a level of
210
A.
36
VCN
A
Analog
Connection for external loop filter components. This is the differential control voltage
input to the internal VCO and the internal differential charge pump output up to a level of
210
A.
40
RESETB
I
LVTTL/
LVCMOSU
Schmitt
Trigger
Active low reset signal with pull up and Schmitt type input. Used to apply an active-low
Power-on Reset (POR) signal during system initialization. Should be connected via a
capacitor to ground.
41
SYNCP
I
LVPECL
Additional differential input (2 kHz or 8 kHz) where the Sync signal on this input is
sampled and resynchronized by clock output OUT1. The resynchronization can be
configured via CFG_IN4 and CFG_IN5 to be with the rising or falling edge of output OUT1;
see Table 12. Will also accept CML or LVDS signal types when used in conjunction with
external biasing components as described in Figures 14 to 19.
42
SYNCN
I
LVPECL
Additional differential input (2 kHz or 8 kHz) where the Sync signal on this input is
sampled and resynchronized by clock output OUT1. The resynchronization can be
configured via CFG_IN4 and CFG_IN5 to be with the rising or falling edge of output OUT1;
see Table 12. Will also accept CML or LVDS signal types when used in conjunction with
external biasing components as described in Figures 14 to 19.
44
SYNC_OUT
O
LVTTL/
LVCMOS
A sampled and therefore lower jitter and resynchronized version of the SYNC signal
selected from the SYNC1 input. The clock selected on OUT1 (see pins 2 and 3) is used to
perform the resynchronization. The resynchronization can be configured to be with the
rising or falling edge of output OUT1; see Table 12. The maximum output frequency on
OUT1 = 77.76 MHz when the Sync function is used.
45
RATE2A
I
LVTTL/
LVCMOSD
Inputs to control the frequency of the signal produced on pins 5 (OUT2P) and 6 (OUT2N).
46
RATE2B
I
LVTTL/
LVCMOSD
Inputs to control the frequency of signal that is produced on pins 5 (OUT2P) and 6
(OUT2N). See Table 11.
47
RATE1A
I
LVTTL/
LVCMOSD
Inputs to control the frequency of signal that is produced on pins 2 (OUT1P) and 3
(OUT1N). See Table 11.
48
RATE1B
I
LVTTL/
LVCMOSD
Inputs to control the frequency of signal that is produced on pins 2 (OUT1P) and 3
(OUT1N). See Table 11.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
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