參數(shù)資料
型號: ACS8946T
廠商: Semtech
文件頁數(shù): 15/40頁
文件大?。?/td> 0K
描述: IC JITTER ATT MULT PLL 48-QFN
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網,SONET/SDH
輸入: LVPECL
輸出: CML,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 625MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應商設備封裝: 48-QFN(7x7)
包裝: 托盤
ADVANCED COMMUNICATIONS
FINAL
DATASHEET
Revision 3/November 2006 Semtech Corp.
Page 22
www.semtech.com
ACS8946 JAM PLL
Applications
The ACS8946 is targeted at applications requiring clock
cleaning, where input jitter is filtered out or attenuated at
frequencies above the ACS8946 PLL bandwidth, and at
those requiring protection switching. It also performs the
function of a clock multiplying unit (CMU) translating from
one common spot frequency to one of six spot
frequencies (and/or odd divisions thereof) independently
on each of its four outputs.
The ACS8946 can save space when compared with
discrete analog + VCXO solutions or module-based
solutions. In the example in Figure 12 the ACS8946 is
shown symbolically as a line card dejittering and clock
multiplying device, providing additional jitter cleaning and
frequency translation of the output clocks from a Semtech
Line Card Protection device.
Figure 13 shows a non-specific example schematic which
represents a generic line card design, and demonstrates
the I/O connections, configuration controls on the device
and the appropriate terminations in different
CML/LVPECL technologies, with only the parts relevant to
the handling of clocks being shown. This example could
be used as a solution for less stringent applications where
the ACS8946 could carry out the basic clock protection
function in place of a Semtech Line Card Protection
device, although it could not, for example, perform group
(Clock and Sync) switching, frequency monitoring, or other
functions available with members of the Semtech LC/P
family of parts.
Application Diagram
Figure 12 Typical Application for Semtech JAM PLLs
Multiple Line cards
Primary Ref.
Input/
output
Master Sync Card
Slave Sync Card
uP/Serial Bus
SSM
Priorities
TCLK
CLK
SEC
Master Clock
DATA
Priorities
Config.
Input CLK Sources
Line
I/F
Unit
SetsLinecardGenApp_11
To/from
SONET/SDH/PDH
Network
FRAMER
SERDES
Line Card (0C-12)
Master Clock
Recovered Clock
Sync
Slave Clock
Backplane
Low Jitter/Low Skew
Low Jitter spot frequencies to 625.00 MHz
Sync
4 x Programmable Clocks
JAM PLL with
PROTECTION
SWITCH
SETS
Output
CLKs
ACS8946
ACS8510
ACS8520
ACS8522
ACS8530
Clock
Distribution
SSM Processing
Slave Clock
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