參數(shù)資料
型號: 9S12XDP512DGV1
英文描述: Device User Guide for Mask Set 0L40V ( First Silicon)
中文描述: 設(shè)備用戶指南掩模組0L40V(第一硅)
文件頁數(shù): 69/152頁
文件大?。?/td> 1231K
代理商: 9S12XDP512DGV1
69
Table 2-1 Signal Properties Summary
Pin Name
Funct. 1
Pin Name
Funct. 2
Pin Name
Funct. 3
Pin Name
Funct. 4
Pin Name
Funct. 5
Power
Supply
Internal Pull
Resistor
Description
CTRL
Reset
State
EXTAL
XTAL
VDDPLL
VDDPLL
NA
NA
NA
NA
Oscillator Pins
RESET
VDDR
PULLUP
External Reset
TEST
N.A.
RESET
PIN
Always
on
DOWN
Test Input
VREGEN
VDDX
Up
Voltage Regulator Enable Input
XFC
VDDPLL
NA
NA
PLL Loop Filter
BKGD
MODC
VDDR
Always
on
PER0
AD1/
PER1
AD1
Up
Background Debug
PAD[23:08]
AN[15:0]
VDDA
Disabled
Port AD Inputs of ATD1, Analog
Inputs of ATD1
PAD[07:00]
AN[7:0]
VDDA
PER1
AD0
Disabled
Port AD Inputs of ATD0, Analog
Inputs of ATD0
Port A I/O, Address Bus, Internal
Visibility Data
Port B I/O, Address Bus, Internal
Visibility Data
Port B I/O, Address Bus, Upper Data
Strobe
Port C I/O, Data Bus
Port D I/O, Data Bus
Port E I/O, System clock output,
Clock Select
PA[7:0]
ADDR[15:8]
IVD[15:8]
VDDR
PUCR
Disabled
PB[7:1]
ADDR[7:1]
IVD[7:0]
VDDR
PUCR
Disabled
PB0
ADDR0
UDS
VDDR
PUCR
Disabled
PC[7:0]
PD[7:0]
DATA[15:8]
DATA[7:0]
VDDR
VDDR
PUCR
PUCR
Disabled
Disabled
PE7
ECLKX2
XCLKS
VDDR
PUCR
Up
PE6
TAGHI
MODB
VDDR
While RESET
pin is low:
Down
While RESET
pin is low:
Down
Port E I/O, Tag High, Mode Input
PE5
RE
MODA
TAGLO
VDDR
Port E I/O, Read Enable, Mode Input,
Tag Low Input
PE4
ECLK
VDDR
PUCR
Up
Port E I/O, Bus Clock Output
Port E I/O, Low Byte Data strobe,
EROMON control
PE3
LSTRB
LDS
EROMCTL
VDDR
PUCR
Up
PE2
R/W
WE
VDDR
PUCR
Up
Port E I/O, Read/Write
PE1
IRQ
VDDR
PUCR
Up
Port E Input, Maskable Interrupt
PE0
XIRQ
VDDR
PUCR
Up
Port E Input, Non Maskable Interrupt
PH7
KWH7
SS2
TXD5
VDDR
PERH/
PPSH
Disabled
Port H I/O, Interrupt, SS of SPI2,
TXD of SCI5
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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