參數(shù)資料
型號： 9S12XDP512DGV1
英文描述： Device User Guide for Mask Set 0L40V ( First Silicon)
中文描述： 設備用戶指南掩模組0L40V（第一硅）
文件頁數(shù)： 38/152頁
文件大小： 1231K
代理商： 9S12XDP512DGV1
MC9S12XDP512 Device User Guide — 9S12XDP512DGV1/D V01.12
38
$00C8 - $00CF
Asynchronous Serial Interface (SCI0) Map
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$00C8
SCI0BDH
1
NOTES
:
1. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to zero
2. Those registers are accessible if the AMAP bit in the SCI0SR2 register is set to one
Read:
Write:
Read:
Write:
Read:
Write:
Read: RXEDGI
Write:
Read: RXEDGI
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
Read:
Write:
IREN
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
$00C9
SCI0BDL
1
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
$00CA
SCI0CR1
1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
$00C8
SCI0ASR1
2
F
0
0
0
0
BERRV
BERRIF
BKDIF
$00C9
SCI0ACR1
2
E
0
0
0
0
0
0
BERRIE
BKDIE
$00CA
SCI0ACR2
2
0
0
0
0
BERRM1 BERRM0
BKDFE
$00CB
SCI0CR2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
$00CC
SCI0SR1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
$00CD
SCI0SR2
AMAP
0
0
TXPOL
RXPOL
BRK13
TXDIR
RAF
$00CE
SCI0DRH
R8
T8
0
0
0
0
0
0
$00CF
SCI0DRL
R7
T7
R6
T6
R5
T5
R4
T4
R3
T3
R2
T2
R1
T1
R0
T0
$00D0 - $00D7
Asynchronous Serial Interface (SCI1) Map
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
$00D0
SCI1BDH
1
Read:
Write:
Read:
Write:
Read:
Write:
Read: RXEDGI
Write:
Read: RXEDGI
Write:
Read:
Write:
Read:
Write:
Read:
Write:
IREN
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
$00D1
SCI1BDL
1
SBR7
SBR6
SBR5
SBR4
SBR3
SBR2
SBR1
SBR0
$00D2
SCI1CR1
1
LOOPS
SCISWAI
RSRC
M
WAKE
ILT
PE
PT
$00D0
SCI1ASR1
2
F
0
0
0
0
BERRV
BERRIF
BKDIF
$00D1
SCI1ACR1
2
E
0
0
0
0
0
0
BERRIE
BKDIE
$00D2
SCI1ACR2
2
0
0
0
0
BERRM1 BERRM0
BKDFE
$00D3
SCI1CR2
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
$00D4
SCI1SR1
TDRE
TC
RDRF
IDLE
OR
NF
FE
PF
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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