參數(shù)資料
型號： 9S12XDP512DGV1
英文描述： Device User Guide for Mask Set 0L40V ( First Silicon)
中文描述： 設(shè)備用戶指南掩模組0L40V（第一硅）
文件頁數(shù)： 129/152頁
文件大?。?/td> 1231K
代理商： 9S12XDP512DGV1
129
A.3.2 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures.
The failure rates for data retention and program/erase cycling are specified at the operating conditions
noted.
The program/erase cycle count on the sector is incremented every time a sector or mass erase event is
executed.
NOTE:
All values shown in
Table A-16
are target values and subject to further extensive
characterization.
3. Maximum Erase and Programming times are achieved under particular combinations of f
NVMOP
and bus frequency f
bus
.
Refer to formulae in Sections
A.3.1.1 - A.3.1.4
for guidance.
4. Burst Programming operations are not applicable to EEPROM
5. Minimum Erase times are achieved under maximum NVM operating frequency f
NVMOP
.
6. Minimum time, if first word in the array is not blank
7. Maximum time to complete check on an erased block
Table A-16 NVM Reliability Characteristics
Conditions are shown in
Table A-4
unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
C
Data Retention at an average junction temperature of
T
Javg
= 70
°
C
t
NVMRET
15
Years
2
C Flash number of Program/Erase cycles
n
FLPE
1000
10,000
Cycles
3
C
EEPROM number of Program/Erase cycles
(–40
°
C
≤
T
J
≤
0
°
C)
n
EEPE
10,000
Cycles
4
C
EEPROM number of Program/Erase cycles
(0
°
C < T
J
≤
140
°
C)
n
EEPE
100,000
Cycles
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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