參數(shù)資料
型號(hào): 9S12XDP512DGV1
英文描述: Device User Guide for Mask Set 0L40V ( First Silicon)
中文描述: 設(shè)備用戶指南掩模組0L40V(第一硅)
文件頁數(shù): 131/152頁
文件大?。?/td> 1231K
代理商: 9S12XDP512DGV1
131
A.4 Voltage Regulator
Table 28-2 Voltage Regulator Electrical Characteristics
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
1
P
Input Voltages
V
VDDR,A
3.15
5.5
V
2
P
Regulator Current
Reduced Power Mode
Shutdown Mode
I
REG
20
12
50
40
μ
A
μ
A
3
P
Output Voltage Core
Full Performance Mode
Reduced Power Mode
Shutdown Mode
V
DD
2.35
1.6
2.5
2.5
1
NOTES
:
1. High Impedance Output
2. Current IDDPLL = 1mA (Colpitts Oscillator)
3. Current IDDPLL = 3mA (Pierce Oscillator)
4. High Impedance Output
5. Monitors V
DDA
, active only in Full Performance Mode. Indicates I/O & ADC performance degradation due to
low supply voltage.
6. Monitors V
DD
, active only in Full Performance Mode. MCU is monitored by the POR in RPM (see
Figure A-1
)
7. Monitors V
DD
. Active in all modes.
2.75
2.75
V
V
V
4
P
Output Voltage PLL
Full Performance Mode
ReducedPowerMode
2
Reduced Power Mode
3
Shutdown Mode
V
DDPLL
2.35
2.0
1.6
2.5
2.5
2.5
4
2.75
2.75
2.75
V
V
V
7
P
Low Voltage Interrupt
5
Assert Level
Deassert Level
V
LVIA
V
LVID
4.1
4.25
4.37
4.52
4.66
4.77
V
V
8
P
Low Voltage Reset
6
Assert Level
V
LVRA
2.25
V
9
C
Power-on Reset
7
Assert Level
Deassert Level
NOTE:
The electrical characteristics given in this section are preliminary and
should be used as a guide only. Values in this section cannot be
guaranteed by Motorola and are subject to change without notice.
V
PORA
V
PORD
0.97
2.05
V
V
12
C
Trimmed API internal clock
f / f
nominal
df
API
- 10%
+ 10%
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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PDF描述
9S12XDP512DGV2 Device User Guide for Mask Set L15Y - (Second Silicon - Enhanced Feature Set)
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