
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 14: FGPI: Fast General Purpose Interface
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
14-22
Table 4: Status Registers
Bit
Symbol
Acces
s
Value
Description
Standard Registers
Offset 0x07,0FE0
FGPI_IR_STATUS
31:8
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
7
BUF1_ACTIVE
R
0
1 when Buffer 1 is active
6
OVERFLOW
R
0
Message Overow Error detected.
5
MBE
R
0
Memory Bandwidth Error detected.
4
UNDERRUN
R
0
Buffer Underrun detected.
3
THRESH2_REACHED
R
0
Buffer 2 Threshold reached.
2
THRESH1_REACHED
R
0
Buffer 1 Threshold reached.
1
BUF2_FULL
R
0
Buffer 2 is full.
0
BUF1_FULL
R
0
Buffer 1 is full.
Offset 0x07,0FE4
FGPI_IR_ENA
31:7
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6
OVERFLOW_ENA
R/W
0
Message Overow Error Interrupt Enable
5
MBE_ENA
R/W
0
Memory Bandwidth Error Interrupt Enable
4
UNDERRUN_ENA
R/W
0
Buffer Underrun Interrupt Enable
3
THRESH2_REACHED_
ENA
R/W
0
Buffer 2 Threshold Interrupt Enable
2
THRESH1_REACHED_
ENA
R/W
0
Buffer 2 Threshold Interrupt Enable
1
BUF2_FULL_ENA
R/W
0
Buffer 2 full Interrupt Enable
0
BUF1_FULL_ENA
R/W
0
Buffer 1 full Interrupt Enable
Offset 0x07,0FE8
FGPI_IR_CLR
31:7
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6
OVERFLOW_ACK
R/W
0
Message Overow Error Interrupt Acknowledge
5
MBE_ACK
R/W
0
Memory Bandwidth Error Interrupt Acknowledge
4
UNDERRUN_ACK
R/W
0
Buffer Underrun Interrupt Acknowledge
3
THRESH2_REACHED_
ACK
R/W
0
Buffer 2 Threshold Interrupt Acknowledge
2
THRESH1_REACHED_
ACK
R/W
0
Buffer 2 Threshold Interrupt Acknowledge
1
BUF2_DONE_ACK
R/W
0
Buffer 2 done Interrupt Acknowledge
0
BUF1_DONE_ACK
R/W
0
Buffer 1 done Interrupt Acknowledge
Offset 0x07,0FEC
FGPI_IR_SET
31:7
Reserved
R
0
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
6
OVERFLOW_SET
R/W
0
Set Message Overow Error Interrupt