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型號(hào)：	935278155557
廠商：	NXP SEMICONDUCTORS
元件分類：	消費(fèi)家電
英文描述：	SPECIALTY CONSUMER CIRCUIT, PBGA456
封裝：	27 X 27 MM, 1.75 MM HIEGHT, PLASTIC, MS-034, BGA-456
文件頁(yè)數(shù)：	197/828頁(yè)
文件大?。?/td>	7748K
代理商：	935278155557

Philips Semiconductors

PNX15xx Series

Volume 1 of 1

Chapter 8: General Purpose Input Output Pins

PNX15XX_SER_3

Product data sheet

Rev. 3 — 17 March 2006

Monitoring continues in DMA buffer 2, until it lls up. At that time,

INT_STATUSx.BUF2_RDY is asserted, monitoring continues in the new DMA buffer

1, and the interrupt needs to be acknowledged as for DMA buffer 1.

If the software fails to read the full DMA buffers in time (i.e BUF1_RDY or BUF1_RDY

is not cleared in time), the overrun error ag, INT_STATUSx.FIFO_OE, is raised and

data may be lost. The INT_STATUSx.FIFO_OE error ag can only be cleared by an

explicit write of ‘1’ to the INT_CLEARx.FIFO_OE_CLR bit. The interrupt if seen by the

TM3260 CPU if the bit INT_ENABLEx.FIFO_OE_EN is set.

If enabled, an interval of silence, GPIO_EVx.INTERVAL, can cause a BUFx_RDY ag

to be asserted before all locations in the DMA buffer have been lled. Therefore,

whenever BUFx_RDY is asserted, software is required to read the relevant

INT_STATUSx register to know exactly how many valid 32-bit words of data are in the

DMA buffer. The INT_STATUSx holds the VALID_PTR eld which gives this

information.

The number of valid 32-bit data words written to the DMA buffers is loaded by the

GPIO module to the VALID_PTR eld of the INT_STATUSx register immediately

before the GPIO sets the relevant BUFx_RDY ag. If a second BUFx_RDY is

activated before the rst ag was cleared, VALID_PTR cannot be updated by the

GPIO until the rst activated BUFx_RDY ag is cleared by software. This clear will

allow the GPIO to load the new VALID_PTR value for the second buffer.

If both BUFx_RDY ags are cleared at the same time, i.e if the value of VALID_PTR is

not needed, the VALID_PTR value points back to the rst buffer whose BUFx_RDY

ag was raised. If the VALID_PTR value is required to be read, each BUFx_RDY

must be cleared individually and in the correct order.

VALID_PTR is stable to be read by software when a BUFx_RDY ag is raised.

BASE1_PTRx should be stable to be loaded by the GPIO module when BUF1_RDY

is cleared by software and BASE2_PTRx should be stable to be loaded by the GPIO

module when BUF2_RDY is cleared by software.

Remark: A DMA buffer can ‘fill up’ in two ways: all available locations are written to,

or, in monitoring timestamped event mode, an interval of silence occurred.

Remark: SIZE must be a multiple of 64 bytes. SIZE is a static configuration register

and should not change during GPIO operation.

The Interval of Silence in Event Timestamping Sampling Mode

If events occur on a monitored signal and an interval of silence follows, the relevant

internal buffer contents are ushed to the DMA buffers.

When the contents of the internal buffer are ushed to the DMA buffer the relevant

BUFx_RDY ag is set. The BUFx_RDY interrupt indicates that the DMA buffer is

ready to be read by software and writing is switched to the second DMA buffer.

When an interval of silence occurs all the 64 bytes of the internal buffer are ushed

even though there may not be 64 bytes of valid data in the internal buffer. Software

must then read the module status to read the address where the last valid 32-bit data

word, INT_STATUSx.VALID_PTR, was written.

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