
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
7-28
15:8
unlock_ssid
W
0
Writing a “0xCA” to this eld will unlock the “subsystem_id” and
“subsystem_vendor” registers. A writer to the subsystem_id/
subsystemvendor” register will lock the register again.
7:0
unlock_setup
W
0
Writing a “0xCA” to this eld will unlock the “classcode”,
“max_latency”, “min_gnt” and “pci_setup” registers. A write to the
“pci_setup” register to lock registers again.
Offset 0x04 0040
Image of Device ID and Vendor ID
31:16
device_id
R
0x5405
PCI conguration device ID
15:0
vendor_id
R
0x1131
PCI conguration vendor ID
Offset 0x04 0044
Image of Command/Status
31:16
status
R
0x0290
PCI conguration status register
15:0
command
R/W*
0x0000
PCI conguration command register.
*This register is read/write if conguration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Refer to conguration register 4 for details on which bits are
implemented and controllable.
Offset 0x04 0048
Image of Class Code/Revision ID
31:8
class code
R/W*
048000
PCI conguration class code.
*Write-once/Read-only
7:0
revision id
R
1
PCI conguration revision ID
Offset 0x04 004C
Image of Latency Timer/Cache Line Size
31:24
BIST
R
0
PCI conguration BIST
23:16
Header Type
R
0
PCI conguration Header Type
15:8
latency timer
R/W*
0
PCI conguration latency timer.
*This register is read/write if conguration management is enabled
(pci_setup[1]). If not enabled, it is read only.
7:0
cache line size
R/W*
0
PCI conguration cache line size.
*This register is read/write if conguration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Offset 0x04 0050
Base Address 10 Image
31:21
Base Address 10
R/W*
0
PCI conguration Base address for DRAM.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if conguration management is enabled
(pci_setup[1]). If not enabled, it is read only.
20:4
Reserved
R
0
3
Prefetchable
R
cfg*
*Value is determined at boot time by pci_setup register.
2:0
Type
R
0
Indicates type 0 memory space (locatable anywhere in 32-bit
address space).
Offset 0x04 0054
Base Address 14 Image
31:4
Base Address 14
R/W*
1BE00000
PCI conguration Base address for MMIO.
This register affects the decode and routing of the bus controllers. It
should not be relied on as stable for 10 clocks after writing.
*This register is read/write if conguration management is enabled
(pci_setup[1]). If not enabled, it is read only.
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description