
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 3: System On Chip Resources
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
3-27
8.1 Miscellaneous System MMIO registers
Table 9: Miscellaneous System MMIO registers
Bit
Symbol
Acces
s
Value
Description
System Registers
Offset 0x06 3050
PCI_INTA
31:2
Unused
-
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
1
PCI_INTA
W
0x1
Writes PCI_INTA_N pin value if PCI_INTA_OE is enabled
0: PCI_INTA_N is 0 (asserted)
1: PCI_INTA_N is 1 (de-asserted)
To read the PCI_INTA_N pin value use IPENDING MMIO register.
0
PCI_INTA_OE
R/W
0x0
Enable of PCI_INTA_N output
0: Disable PCI_INTA_N output
1: Enable PCI_INTA_N output
Note: In order to operate the PCI_INTA_N pin as an open drain pin
as required by the PCI specication, the software must enable the
output only when driving a ‘0’, i.e. asserting an interrupt.
Note: In order to avoid a race condition between the data and the
enable or glitches on the PCI_INTA_N pin, the enable should only
be changed once the data is stable.
Offset 0x06 3500
SCRATCH0
31:0
SCRATCH0
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.
Offset 0x06 3504
SCRATCH1
31:0
SCRATCH1
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.
Offset 0x06 3508
SCRATCH2
31:0
SCRATCH2
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.
Offset 0x06 350C
SCRATCH3
31:0
SCRATCH3
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.
Offset 0x06 3510
SCRATCH4
31:0
SCRATCH4
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.
Offset 0x06 3514
SCRATCH5
31:0
SCRATCH5
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.
Offset 0x06 3518
SCRATCH6
31:0
SCRATCH6
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.
Offset 0x06 351C
SCRATCH7
31:0
SCRATCH7
R/W
-
32-bit writable and readable register. Not cleared at reset for debug
purposes.