
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 20: 2D Drawing Engine
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
20-25
W[11:0] species the width of a BLT in pixels. The minimum allowed value is 1 and
the maximum value is 4k-1. Zero is not a valid value for this eld. W[11:0]
corresponds to bits 11:0 of this register. H[11:0] species the height of a BLT in lines.
The minimum allowed value is 1 and the maximum value is 4k-1. Zero is not a valid
value for this eld. H[11:0] corresponds to bits 27:16 of this register.
Note that loading the high byte of this register starts a BLT or Alpha Blending
operation. This register is unchanged by any drawing operations.
This register is used to load the starting XY pixel destination coordinate for a drawing
operation.
The X and Y elds are unsigned 11-bit numbers allowing a 2K by 2K address space.
Since the drawing engine uses linear addresses internally, the X and Y coordinates in
this register will be converted to a linear address. It is byte accessible; a write to the
high byte of this register begins the conversion process from XY to linear.
This register causes the same behavior as writing to DstXY, which is provided to
allow for command register bursting during BitBlt commands.
Drawing commands that require the use of patterns must use this register to specify
the destination coordinate. Using the DstLinear register to specify the destination
during a pattern command will cause errant results. Also loads the DstLinear register
with the converted XY address.
This register holds the two error term values for the Bresenham line algorithm. These
values are computed by the host processor as follows:
Const0 = 2 x dmin - 2 x dmax
Table 24: Destination Address, XY2 Coordinates
Bit
Symbol
Acces
s
Value
Description
Offset 0x04 F438
Destination Address, XY2 Coordinates
31:27
Reserved
26:24
Y[10:8]
R/W
0
Unsigned 11-bit Y destination address
23:16
Y[7:0]
R/W
0
15:11
Reserved
10:8
X[10:8]
R/W
0
Unsigned 11-bit X destination address
7:0
X[7:0]
R/W
0
Table 25: Vector Constant
Bit
Symbol
Acces
s
Value
Description
Offset 0x04 F43C
Vector Constant
31:24
Const1 [15:8]
R/W
0
Const1 = 2 x dmin
23:16
Const1 [7:0]
R/W
0
15:8
Const0 [15:8]
R/W
0
Const0 = 2 x dmin - 2 x dmax
7:0
Const0 [7:0]
R/W
0