
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 1: Integrated Circuit Data
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
1-15
AO_WS
AE20
BPTS3CHP
I/O
21
U AO can operate in either master or slave mode.
When Audio-Out is programmed as the serial-
interface timing slave (power-up default),
AO_WS acts as an input. AO_WS is sampled on
the opposite AO_SCK edge at which
AO_SD[3:0] are asserted.
When Audio Out is programmed as serial-
interface timing master, AO_WS acts as an
output. AO_WS is asserted on the same
AO_SCK edge as AO_SD[3:0].
AO_WS is the word-select or frame-
synchronization signal from/to the external D/A
subsystem. Each audio channel receives 1 sample
for every WS period.
AO_SD3
AO_SD2
AO_SD1
AO_SD0
AF21
AF20
AE19
AF19
BPTS3CHP
OUT
25
24
23
22
U
Serial Data to external audio D/A subsystem for rst
2 of 8 channels. The timing of the transitions on
these outputs is determined by the CLOCK_EDGE
bit in the AO_SERIAL register, and can be on a
positive or negative AO_SCK edge.
SPDIF interface
SPDI
A6
BPT3MCHDT5V
IN
56
D Input for SPDIF (Sony/Philips Digital Audio
Interface, a.k.a. Dolby DigitalTM), a self clocking
audio data stream as per IEC958 with 1937
extensions. This pin is 5 V tolerant input.
SPDO
AF22
BPX2T14MCP
OUT
57
U Output for SPDIF. Note that this low-impedance
driver requires a 27-33
resistor close to the
PNX1500 to match the board line impedance. This
resistor becomes a part of the voltage divider
necessary to drive the IEC958 isolation
transformer.
10/100 LAN interface (MII)
LAN_CLK
AF18
BPTS1CP
OUT
-
U Clock to feed the external PHY, usually 50 MHz.
LAN_TX_CLK/
LAN_REF_CLK
AF14
BPTS3CP
IN
-
U MII Transmit clock or RMII reference clock. Both
LAN_TX_CLK and LAN_RX_CLK have to be
connected to the RMII reference clock in RMII
mode.
LAN_TX_EN
AD13
BPTS3CHP
OUT
35
D MII or RMII Transmit Enable
LAN_TXD3
LAN_TXD2
LAN_TXD1
LAN_TXD0
AF15
AD14
AC15
AE14
BPTS3CHP
OUT
39
38
37
36
D
MII Transmit Data
MII or RMII Transmit Data
LAN_TX_ER
AE13
BPTS3CHP
OUT
40
D MII Transmit Error
LAN_CRS/
LAN_CRS_DV
AC24
BPT3MCHDT5V
IN
41
D MII Carrier Sense or RMII Carrier Sene and
Receive Data Valid. This pin is 5 V tolerant input.
LAN_COL
AA23
BPT3MCHDT5V
IN
42
D Collision Detect. This pin is 5 V tolerant input.
Table 4: PNX1500 Interface
Pin Name
BGA
Ball
Pad
Type
I/O
Type
GPIO
#
P Description