
Philips Semiconductors
PNX15xx Series
Volume 1 of 1
Chapter 7: PCI-XIO Module
PNX15XX_SER_3
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 3 — 17 March 2006
7-25
20:18
base18_siz
R/W1
011
The size of aperture located by PCI cfg base18 is:
011 = 16 MB
100 = 32 MB
101 = 64 MB
110 = 128 MB
This aperture is used as the XIO aperture in the PNX15xx Series.
Note: If expanding to 128 MB, the default setting of base18 address
will overlap with the default base14 address. To avoid an address
conict, the base18 address or the base14 address should be
relocated before setting the base18_siz.
17
en_base18
R/W1
1
Enable 3rd aperture, PCI base address 18. The PNX15xx Series
will always use this aperture.
16
base14_prefetchable
R/W1
0
PCI Base address 14 is a non-prefetchable memory aperture.
15
Reserved
R
0
14:12
base14_siz
R/W1
000
The size of aperture located by PCI cfg base 14 is 000 = 2 MB.
This aperture is used as the MMIO aperture in the PNX15xx Series.
11
en_base14
R/W1
1
Enable 2nd aperture, PCI base address 14. The PNX15xx Series
will always use this aperture.
10
base10_prefetchable
R/W1
1
PCI Base address 10 is a prefetchable memory aperture.
9:7
base10_siz
R/W1
100
The size of aperture located by PCI cfg base 10 is:
011 = 16 MB
100 = 32 MB
101 = 64 MB
110 = 128 MB
This aperture is used as the DRAM aperture in the PNX15xx
Series.
6:2
Reserved
1
en_cong_manag
R/W1
1
Enable conguration management.
0
en_pci_arb
R/W1
0
Enable internal PCI system arbitration.
Offset 0x04 0014
PCI Control
31:17
Reserved
R
0
16
dis_swapper2targ
R/W
0
0 = Enable byte swapping in big endian mode from DCS to PCI
path.
1 = Disable byte swapping in big endian mode from DCS to PCI
path.
15
dis_swapper2intreg
R/W
0
0 = Enable byte swapping in big endian mode from PCI to PCI mmio
registers.
1 = Disable byte swapping in big endian mode from PCI to PCI
mmio registers.
14
dis_swapper2dtlinit
R/W
0
0 = Enable byte swapping in big endian mode from PCI to DCS.
1 = Disable byte swapping in big endian mode from PCI to DCS.
13
regs_wr_post_en
R/W
0
Enable write posting to internal PCI registers.
12
xio_wr_post_en
R/W
0
Enable write posting to XIO address range.
11
pci2_wr_post_en
R/W
0
Enable write posting to pci_base2 address range.
Table 8: Registers Description
Bit
Symbol
Acces
s
Value
Description